AD73311LAR Analog Devices Inc, AD73311LAR Datasheet - Page 7

• Manufacturer Part Number: AD73311LAR
• Description: IC ANALOG FRONT END 20-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73311LAR

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 2
• Power (watts): 50mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 20-SOIC (7.5mm Width)
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.3V
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Not Compliant

Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Mnemonic
VOUTP
VOUTN
AVDD1
AGND1
VINP
VINN
REFOUT
REFCAP
AVDD2
AGND2
DGND
DVDD
RESET
SCLK
MCLK
SDO
SDOFS
SDIFS
SDI
SE
Function
Analog Output from the Positive Terminal of the Output Channel.
Analog Output from the Negative Terminal of the Output Channel.
Analog Power Supply Connection for the Output Driver.
Analog Ground Connection for the Output Driver.
Analog Input to the Positive Terminal of the Input Channel.
Analog Input to the Negative Terminal of the Input Channel.
Buffered Reference Output, which has a nominal value of 1.2 V.
A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should
be fixed to this pin.
Analog Power Supply Connection.
Analog Ground/Substrate Connection.
Digital Ground/Substrate Connection.
Digital Power Supply Connection.
Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing
the digital circuitry.
Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock
data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to
the frequency of the master clock (MCLK) divided by an integer number—this integer number being
the product of the external master clock rate divider and the serial clock rate divider.
Master Clock Input. MCLK is driven from an external clock signal.
Serial Data Output of the Codec. Both data and control information may be output on this pin and are
clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted
and when SE is low.
Framing Signal Output for SDO Serial Transfers. The frame sync is on bit wide and is active one
SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive
edge of SCLK. SDOFS is in three-state when SE is low.
Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one
SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of
SCLK and ignored when SE is low.
Serial Data Input of the Codec. Both data and control information may be input on this pin and are
clocked on the negative edge of SCLK. SDI is ignored when SE is low.
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the
output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled
internally in order to decrease power dissipation. When SE is brought high, the control and data regis-
ters of the SPORT are at their original values (before SE was brought low); however, the timing
counters and other internal registers are at their reset values.
PIN FUNCTION DESCRIPTIONS
AD73311L