AD73311LAR Analog Devices Inc, AD73311LAR Datasheet - Page 4

• Manufacturer Part Number: AD73311LAR
• Description: IC ANALOG FRONT END 20-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73311LAR

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 2
• Power (watts): 50mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 20-SOIC (7.5mm Width)
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.3V
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Not Compliant

AD73311L
Parameter
V
V
ADC
DAC
TIMING CHARACTERISTICS
Parameter
Clock Signals
Serial Port
REFCAP
REFOUT
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
t
2
Condition
Maximum Input Range at V
Nominal Reference Level
Maximum Voltage
Output Swing
Nominal Voltage
Differential
Output Bias Voltage
Limit at
T
61
24.4
24.4
t
0.4 × t
0.4 × t
20
0
10
10
10
10
30
t
1
1
Single-Ended
Differential
Output Swing
Single-Ended
A
= –40 C to +105 C
SCLK
MCLK
1
1
t
3
(AVDD = DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; T
*
t
13
*
SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY (MCLK/4 SHOWN HERE).
Table II. Signal Ranges
t
1
IN
t
5
t
4
t
2
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
t
6
TO OUTPUT
t
3
PIN
15pF
A
C
= T
L
Description
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
Signal Range
1.2 V ± 10%
1.2 V ± 10%
1.578 V p-p
1.0954 V p-p
1.578 V p-p
3.156 V p-p
1.0954 V p-p
2.1909 V p-p
V
MlN
REFOUT
100 A
100 A
to T
MAX
, unless otherwise noted)
I
I
OH
OL
2.1V