ISL12032IVZ Intersil, ISL12032IVZ Datasheet - Page 23

• Manufacturer Part Number: ISL12032IVZ
• Description: IC RTC LP BATT BACK SRAM 14TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL12032IVZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs are the device identifier. These bits
are “1101111b” for the RTC registers and “1010111b” for the
User SRAM.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, then a
read operation is selected. A “0” selects a write operation
(refer to Figure 9).
After loading the entire Slave Address Byte from the SDA bus,
the ISL12032 compares the device identifier and device select
bits with “1101111b” or “1010111b”. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The word
address is either supplied by the master device or obtained
from an internal counter. On power up the internal address
counter is set to address 00h, so a current address read starts
at address 00h. When required, as part of a random read, the
master must supply the 1 Word Address Byte as shown in
Figure 9.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the Control/Status Registers, the slave byte
must be “1101111x” in both places.
A7
D7
1
FIGURE 9. SLAVE ADDRESS, WORD ADDRESS, AND DATA
FROM THE
SIGNALS
MASTER
SIGNALS FROM
SIGNAL AT
A6
D6
1
THE SLAVE
SDA
A5
D5
0
BYTES
S
A
R
T
T
A4
D4
1
1
IDENTIFICATION
1
BYTE WITH
A3
D3
0
1
R/W=0
1 1 1 1
23
1
A2
D2
FIGURE 10. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
0
1
A1
D1
A
C
K
R/W
A0
D0
ADDRESS
BYTE
SLAVE
ADDRESS BYTE
WORD ADDRESS
DATA BYTE
A
C
K
ISL12032
S
A
R
T
T
IDENTIFICATION
1
BYTE WITH
1
R/W = 1
0
1 1 1 1
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL12032 responds with an ACK. At this time, the I
interface enters a standby state.
A multiple byte operation within a page is permitted. The
Address Byte must have the start address, and the data
bytes are sent in sequence after the address byte, with the
ISL12032 sending an ACK after each byte. The page write is
terminated with a STOP condition from the master. The
pages within the ISL12032 do not support wrapping around
for page read or write operations.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure 10). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the RW bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the RW bit set to “1”. After each of the
three bytes, the ISL12032 responds with an ACK. Then the
ISL12032 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (see Figure 10).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointers initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the last memory location in a section or page,
the master should issue a STOP. Bytes that are read at
addresses higher than the last address in a section may be
erroneous.
1
A
C
K
FIRST READ
DATA BYTE
A
C
K
A
C
K
LAST READ
DATA BYTE
April 16, 2009
2
C
FN6618.2
S
O
P
T