ISL12032IVZ Intersil, ISL12032IVZ Datasheet - Page 21

• Manufacturer Part Number: ISL12032IVZ
• Description: IC RTC LP BATT BACK SRAM 14TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL12032IVZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Example 1
• Alarm set with single interrupt (IM = ”0”)
• A single alarm will occur on January 1 at 11:30am.
• Set Alarm registers as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30 a.m. on January 1 (after
seconds changes from 59 to 00) by setting the ALM0 bit in the
status register to “1” and also bringing the IRQ output LOW.
Example 2
• Pulsed interrupt once per minute (IM = ”1”)
• Interrupts at one minute intervals when the seconds
• Set Alarm registers as follows:
Once the registers are set, the following waveform will be
seen at IRQ:
REGISTER
REGISTER
ALARM
register is at 30 seconds.
ALARM
MOA0
DWA0
MNA0
HRA0
SCA0
MNA0
MOA0
DWA0
DTA0
SCA0
HRA0
DTA0
RTC AND ALARM REGISTERS ARE BOTH “30s”
7 6 5 4 3 2 1 0 HEX
0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0
1 0 0 1 0 0 0 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0 HEX
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
0 0 0 0 0 0 0 0 00h Minutes disabled
0 0 0 0 0 0 0 0 00h Hours disabled
0 0 0 0 0 0 0 0 00h Date disabled
0 0 0 0 0 0 0 0 00h Month disabled
0 0 0 0 0 0 0 0 00h Day of week disabled
FIGURE 5. IRQ WAVEFORM
BIT
BIT
60s
21
B0h Minutes set to 30,
00h Seconds disabled
91h Hours set to 11,
81h Date set to 1,
81h Month set to 1,
00h Day of week
enabled
DESCRIPTION
enabled
enabled
enabled
enabled
disabled
DESCRIPTION
ISL12032
Note that the status register ALM0 bit will be set each time
the alarm is triggered, but does not need to be read or
cleared.
Time Stamp V
The TSV2B section bytes are identical to the RTC register
section, except they do not extend beyond the Month. The
Time Stamp captures the FIRST V
transition time, and will not update upon subsequent events,
until cleared (only the first event is captured before clearing).
Set CLRTS = 1 to clear this register (Addr 11h, PWRVDD
register).
Time Stamp Battery to V
The Time Stamp Battery to V
to the RTC section bytes, except they do not extend beyond
Month. The Time Stamp captures the LAST transition of
VBAT to V
power up/down events is retained). Set CLRTS = 1 to clear
this register (Addr 11h, PWRVDD register).
Time Stamp Event Registers (TSEVT)
The TSEVT section bytes are identical to the RTC section
bytes, except they do not extend beyond the Month. The Time
Stamp captures the first event and the most recent three
events. The first event Time Stamp will not update until cleared.
All 4 Time Stamps are all cleared to “0” when writing the event
counter (0Bh) is set to “0”.
Note: The time stamp registers are cleared to all “0”,
including the month and day, which is different from the RTC
and alarm registers (those registers default to 01h). This is
the indicator that no time stamping has occurred since the
last clear or initial power-up. Once a time stamp occurs,
there will be a non-zero time stamp.
User Memory Registers (accessed by
using Slave Address 1010111x)
Addresses [00h to 7Fh]
These registers are 128 bytes of battery-backed user SRAM.
Writes to this section do not need to be proceeded by setting
the WRTC bit.
I
The ISL12032 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12032 operates as a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
2
C Serial Interface
DD
(only the last power up event of a series of
DD
to Battery Registers (TSV2B)
2
DD
DD
C interface is conducted by
section bytes are identical
DD
Registers (TSB2V)
to Battery Voltage
April 16, 2009
FN6618.2