ISL12032IVZ Intersil, ISL12032IVZ Datasheet - Page 22

• Manufacturer Part Number: ISL12032IVZ
• Description: IC RTC LP BATT BACK SRAM 14TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL12032IVZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 6). On power-up of the ISL12032, the SDA pin is in
the input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL12032 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 6). A START condition is ignored during the power-up
sequence.
All I
condition, which is a LOW to HIGH transition of SDA while
2
2
C interface operations must begin with a START
C interface operations must be terminated by a STOP
SDA OUTPUT FROM
SDA OUTPUT FROM
TRANSMITTER
SCL FROM
RECEIVER
SDA
SCL
MASTER
SIGNALS FROM
SIGNAL AT SDA
SIGNALS FROM
THE MASTER
THE ISL12032
22
FIGURE 8. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
START
FIGURE 6. VALID DATA CHANGES, START AND STOP CONDITIONS
START
FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER
HIGH IMPEDANCE
S
T
A
R
T
1
IDENTIFICATION
1
1
0
BYTE
1
STABLE
1 1 1
DATA
ISL12032
0
WRITE
A
C
K
CHANGE
DATA
0 0 0 0
ADDRESS
SCL is HIGH (see Figure 6). A STOP condition at the end of
a read operation or at the end of a write operation to memory
only places the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 7).
The ISL12032 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL12032 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
BYTE
STABLE
DATA
A
C
K
8
DATA
BYTE
HIGH IMPEDANCE
STOP
ACK
9
A
C
K
S
T
O
P
April 16, 2009
FN6618.2