M48T129V-85PM1 STMicroelectronics, M48T129V-85PM1 Datasheet - Page 8

• Manufacturer Part Number: M48T129V-85PM1
• Description: IC TIMEKPR NVRAM 1MBIT 3V 32-DIP
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T129V-85PM1

• Memory Size: 1M (128K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP (600 mil) Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2835-5

Operating modes
2.1
Figure 4.
Figure 5.
8/28
A0-A16
DQ0-DQ7
A0-A16
E
G
DQ0-DQ7
READ mode
The M48T129Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the 17 address inputs defines which one of
the 131,072 bytes of data is to be accessed. Valid data will be available at the data I/O pins
within t
E and G access times are also satisfied. If the E and G access times are not met, valid data
will be available after the latter of the chip enable access times (t
access time (t
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before t
the address inputs are changed while E and G remain active, output data will remain valid
for t
Chip enable or output enable controlled, READ mode AC waveforms
Address controlled, READ mode AC waveforms
AXQX
AVQV
(output data hold time) but will go indeterminate until the next address access.
DATA VALID
(address access time) after the last address input signal is stable, providing the
GLQV
AVQV
tAXQX
).
, the data lines will be driven to an indeterminate state until t
tAVQV
tELQX
tGLQX
tELQV
tAVQV
tGLQV
Doc ID 5710 Rev 4
VALID
tAVAV
VALID
tAVAV
DATA OUT
tAXQX
DATA VALID
tGHQZ
ELQV
M48T129V, M48T129Y
) or output enable
tEHQZ
AVQV
AI01197
AI02324
. If