M48T129V-85PM1 STMicroelectronics, M48T129V-85PM1 Datasheet - Page 7

• Manufacturer Part Number: M48T129V-85PM1
• Description: IC TIMEKPR NVRAM 1MBIT 3V 32-DIP
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T129V-85PM1

• Memory Size: 1M (128K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP (600 mil) Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2835-5

M48T129V, M48T129Y
2
Note:
Operating modes
Figure 3 on page 6
oscillator. The clock locations contain the century, year, month, date, day, hour, minute, and
second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and
31 day months are made automatically. The nine clock bytes (1FFFFh-1FFF9h and 1FFF1h)
are not the actual clock counters, they are memory locations consisting of BiPORT™
READ/WRITE memory cells within the static RAM array.
The M48T129Y/V includes a clock control circuit which updates the clock bytes with current
information once per second. The information can be accessed by the user in the same
manner as any other location in the static memory array. Byte 1FFF8h is the clock control
register. This byte controls user access to the clock information and also stores the clock
calibration setting.
Byte 1FFF7h contains the watchdog timer setting. The watchdog timer can generate either a
reset or an interrupt, depending on the state of the watchdog steering bit (WDS). Bytes
1FFF6h-1FFF2h include bits that, when programmed, provide for clock alarm functionality.
Alarms are activated when the register content matches the month, date, hours, minutes,
and seconds of the clock registers. Byte 1FFF1h contains century information. Byte 1FFF0h
contains additional flag information pertaining to the watchdog timer, the alarm condition
and the battery status. The M48T129Y/V also has its own power-fail detect circuit. This
control circuitry constantly monitors the supply voltage for an out of tolerance condition.
When V
external SRAM, providing data security in the midst of unpredictable system operation. As
V
switches to the battery, maintaining data and clock operation until valid power is restored.
Table 2.
1. See
X = V
Deselect
WRITE
READ
READ
Deselect
Deselect
CC
Mode
falls below battery backup switchover voltage (V
IH
Table 12 on page 23
CC
or V
is out of tolerance, the circuit write protects the TIMEKEEPER
V
IL
Operating modes
SO
; V
4.5 to 5.5V
3.0 to 3.6V
to V
SO
≤ V
V
illustrates the static memory array and the quartz controlled clock
PFD
= battery backup switchover voltage.
or
SO
CC
(1)
(min)
for details.
(1)
Doc ID 5710 Rev 4
V
V
V
V
E
X
X
IH
IL
IL
IL
V
V
G
X
X
X
X
IH
IL
V
V
V
W
X
X
X
IH
IH
IL
SO
), the control circuitry automatically
High Z
High Z
High Z
High Z
DQ0-
D
DQ7
D
OUT
IN
Battery backup mode
CMOS standby
®
Operating modes
register data and
Standby
Power
Active
Active
Active
7/28