M48T129V-85PM1 STMicroelectronics, M48T129V-85PM1 Datasheet - Page 10

• Manufacturer Part Number: M48T129V-85PM1
• Description: IC TIMEKPR NVRAM 1MBIT 3V 32-DIP
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T129V-85PM1

• Memory Size: 1M (128K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP (600 mil) Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2835-5

Operating modes
2.2
Figure 6.
Figure 7.
10/28
A0-A16
E
W
DQ0-DQ7
A0-A16
E
W
DQ0-DQ7
WRITE mode
The M48T129Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable)
are low state after the address inputs are stable.
The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE
is terminated by the earlier rising edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for a minimum of t
t
must be valid t
should be kept high during WRITE cycles to avoid bus contention; although, if the output bus
has been activated by a low on E and G a low on W will disable the outputs t
falls.
WRITE enable controlled, WRITE AC waveforms
Chip enable controlled, WRITE AC waveforms
WHAX
from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in
DVWH
tAVEL
tAVEL
tAVWL
tAVWL
prior to the end of WRITE and remain valid for t
tWLQZ
Doc ID 5710 Rev 4
tAVWH
tWLWH
VALID
tAVAV
VALID
tAVAV
tELEH
tDVWH
tDVWH
DATA INPUT
DATA INPUT
tWHDX
tWHDX
EHAX
tWHQX
tEHAX
tWHAX
WHDX
M48T129V, M48T129Y
from chip enable or
afterward. G
WLQZ
after W
AI02382
AI02582