LMK03002CISQ/NOPB National Semiconductor, LMK03002CISQ/NOPB Datasheet - Page 12

• Manufacturer Part Number: LMK03002CISQ/NOPB
• Description: IC CLOCK CONDITIONER PLL 48-LLP
• Manufacturer: National Semiconductor
• Type: Clock Conditionerr

Specifications of LMK03002CISQ/NOPB

• Pll: Yes
• Input: Clock
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.724GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Frequency-max: 1.724GHz
• For Use With: LMK03002CEVAL - PRECISION CLOCK CONDITIONER WITH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMK03002CISQTR

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2.0 General Programming
Information
The LMK03002/LMK03002C devices are programmed using
several 32-bit registers which control the device's operation.
The registers consist of a data field and an address field. The
last 4 register bits, ADDR[3:0] form the address field. The re-
maining 28 bits form the data field DATA[27:0].
During programming, LEuWire is low and serial data is
clocked in on the rising edge of CLKuWire (MSB first). When
LEuWire goes high, data is transferred to the register bank
selected by the address field. Only registers R0, R4 to R8,
R11, and R13 to R15 need to be programmed for proper de-
vice operation. After programming, CLKuWire, DATAuWire,
LEuWire should remain low to prevent spurious.
For the frequency calibration algorithm to work properly OS-
Cin must be driven by a valid signal when R15 is programmed.
Any changes to the PLL R divider or OSCin require R15 to be
programmed again to activate the frequency calibration rou-
tine.
2.1 RECOMMENDED PROGRAMMING SEQUENCE
The recommended programming sequence involves pro-
gramming R0 with the reset bit set (RESET = 1) to ensure the
device is in a default state. Registers are programmed in order
with R15 being the last register programmed. An example
programming sequence is shown below.
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Program R0 with the reset bit set (RESET = 1). This
ensures the device is in a default state.
Program R4 to R7 as necessary with desired clocks with
appropriate enable, mux, divider, and delay settings.
Program R8 for optiumum phase noise performance.
Program R9 with Vboost setting if necessary. Optional,
only needed to set Vboost = 1.
Program R11 with DIV4 setting if necessary.
Program R13 with oscillator input frequency and internal
loop filter values.
Program R14 with Fout enable bit, global clock output bit,
power down setting, PLL mux setting, and PLL R divider.
Program R15 with PLL charge pump gain, VCO divider,
and PLL N divider. Also starts frequency calibration
routine.
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