MAX3676EHJ Maxim Integrated Products, MAX3676EHJ Datasheet - Page 7

• Manufacturer Part Number: MAX3676EHJ
• Description: IC RECOV/RETIME 622MBPS 32-TQFP
• Manufacturer: Maxim Integrated Products
• Type: Clock and Data Recovery (CDR)r

Specifications of MAX3676EHJ

• Input: PECL
• Output: PECL
• Frequency - Max: 622MHz
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Frequency-max: 622MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

_______________Detailed Description
The block diagram in Figure 1 shows the MAX3676’s
architecture. It consists of a limiting-amplifier input
stage followed by a fully integrated clock/data-recovery
(CDR) block implemented with a PLL. The input stage
is selectable between a limiting amplifier or a simple
PECL input buffer. The limiting amplifier provides an
LOP monitor and an RSSI output. The PLL consists of a
phase/frequency detector (PFD), a loop filter amplifier,
and a voltage-controlled oscillator (VCO).
The MAX3676’s on-chip limiting amplifier accepts an
input signal level from 3.0mV
er consists of a cascade of gain stages that include full-
wave logarithmic detectors. The combined small-signal
gain is approximately 42dB, and the -3dB bandwidth is
650MHz. Input-referred noise is typically 80μV
Figure 1. Functional Diagram
INSEL
DDI+
DDI-
ADI+
ADI-
PECL
LIMITER
42dB
OLC+
CORRECTION
OFFSET
Data-Retiming IC with Limiting Amplifier
LOL
_______________________________________________________________________________________
OLC-
V
CC
6kΩ
P-P
DETECT
POWER
CFILT
622Mbps, 3.3V Clock-Recovery and
Limiting Amplifier
to 1.2V
BIAS
RSSI
1.23V
P-P
INV
PHASE/FREQ
. The amplifi-
DETECTOR
RMS
, pro-
VTH
PHADJ+
Σ
PHADJ-
viding excellent sensitivity for small-amplitude data
streams.
In addition to driving the CDR, the limiting amplifier pro-
vides both an RSSI output and an LOP monitor that
allow the user to program the threshold voltage. The
RSSI circuitry provides an output voltage that is linearly
proportional to the input power (in decibels) detected
between the ADI+ and ADI- input pins and is sensitive
enough to reliably detect signals as small as 2mV
(see the Typical Operating Characteristics ).
Input DC offset reduces the accuracy of the power
detector; therefore, an integrated feedback loop is
included that automatically nulls the input offset of the
gain stage. The addition of this offset-correction loop
requires that the input signal be AC-coupled when
using the ADI+ and ADI- inputs.
Finally, for applications that do not require the limiting
amplifier, selecting the digital inputs conserves power
by turning off the postamplifier block.
FIL+ FIL-
FILTER
V
CC
6kΩ
LOP
622.08MHz
VCO
MAX3676
Q
I
D
Q
PECL
PECL
SDO+
SDO-
SCLKO+
SCLKO-
P-P
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