MAX3676EHJ Maxim Integrated Products, MAX3676EHJ Datasheet - Page 6

IC RECOV/RETIME 622MBPS 32-TQFP

MAX3676EHJ

Manufacturer Part Number
MAX3676EHJ
Description
IC RECOV/RETIME 622MBPS 32-TQFP
Manufacturer
Maxim Integrated Products
Type
Clock and Data Recovery (CDR)r
Datasheet

Specifications of MAX3676EHJ

Input
PECL
Output
PECL
Frequency - Max
622MHz
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-TQFP, 32-VQFP
Frequency-max
622MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
6
18, 21, 31
9, 12, 15,
4, 8, 16,
24, 25
_______________________________________________________________________________________
PIN
10
11
13
14
17
19
20
22
23
26
27
28
29
30
32
1
2
3
5
6
7
SCLKO+
PHADJ+
SCLKO-
PHADJ-
NAME
OLC+
SDO+
INSEL
CFILT
SDO-
OLC-
DDI+
ADI+
RSSI
GND
FIL+
DDI-
ADI-
VTH
LOP
V
LOL
FIL-
INV
CC
Positive Offset-Correction Loop Capacitor Input
Negative Offset-Correction Loop Capacitor Input
Received-Signal-Strength Indicator Output
Supply Ground
Op Amp Inverting Input. Attach to ground if op amp is not used.
Voltage Threshold Input. Threshold voltage for loss-of-power monitor. Attach to V
is not used.
Loss-of-Power Output, TTL. Limiting amplifier loss-of-power monitor. Asserts high when input signal
is below threshold set by VTH.
Positive Supply Voltage
Negative Serial-Clock Output, PECL, 622.08MHz. SDO- is clocked out on the falling edge of SCLKO-.
Positive Serial-Clock Output, PECL, 622.08MHz. SDO+ is clocked out on the rising edge of SCLKO+.
Negative Serial-Data Output, PECL, 622.08Mbps
Positive Serial-Data Output, PECL, 622.08Mbps
Loss-of-Lock Output, TTL. PLL loss-of-lock monitor, active low (see the Design Procedure section).
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to V
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to V
Negative Filter Input. PLL loop filter connection. Connect a 2.2μF capacitor between FIL- and FIL+.
Positive Filter Input. PLL loop filter connection. Internally connected to V
Positive Digital Data Input, PECL, 622.08Mbps serial-data stream
Negative Digital Data Input, PECL, 622.08Mbps serial-data stream
Input Select. Connect to GND to select digital data inputs or V
Negative Analog Data Input, 622.08Mbps serial-data stream
Positive Analog Data Input, 622.08Mbps serial-data stream
RSSI Filter Capacitor Input. Connect a 47nF capacitor between CFILT and V
FUNCTION
CC
for analog data inputs.
CC
.
Pin Description
CC
.
CC
CC
if LOP function
CC
if not used.
if not used.

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