MAX3676EHJ Maxim Integrated Products, MAX3676EHJ Datasheet - Page 10

• Manufacturer Part Number: MAX3676EHJ
• Description: IC RECOV/RETIME 622MBPS 32-TQFP
• Manufacturer: Maxim Integrated Products
• Type: Clock and Data Recovery (CDR)r

Specifications of MAX3676EHJ

• Input: PECL
• Output: PECL
• Frequency - Max: 622MHz
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Frequency-max: 622MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note that the LOL monitor is only valid when a data
stream is present on the inputs to the MAX3676. As a
result, LOL does not detect a loss-of-power condition
resulting from a loss of the incoming signal. See the
Loss-of-Power Monitor section for this type of indicator.
The MAX3676 digital data and clock I/Os (DDI+, DDI-,
SDO+, SDO-, SCLK+, and SCLK-) are designed to
interface with PECL signal levels. It is important to bias
these ports appropriately. A circuit that provides a
Thevenin equivalent of 50Ω to V
with fixed-impedance transmission lines for proper ter-
mination. Make sure that the differential outputs have
balanced loads.
The digital data input signals (DDI+ and DDI-) are dif-
ferential inputs to an emitter-coupled pair. As a result,
the MAX3676 can accept differential input signals as
low as 250mV. These inputs can also be driven single-
ended by externally biasing DDI- to the center of the
voltage swing.
The MAX3676’s performance can be greatly affected
by circuit board layout and design. Use good high-fre-
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
Figure 4. Loss-of-Lock Output
10
______________________________________________________________________________________
NO DATA
LOP
LOL
Input and Output Terminations
ACQUIRE
TIME
LOCKED
CC
- 2V should be used
quency design techniques, including minimizing
ground inductance and using fixed-impedance trans-
mission lines on the data and clock signals. Power-sup-
ply decoupling should be placed as close to V
possible. Take care to isolate the input from the output
signals to reduce feedthrough.
There are three important requirements for driving the
limiting amplifier from a single-ended source (Figure 5):
1) There must be no DC-coupling to the ADI+ and ADI-
2) The terminating resistor R
3) The low-frequency cutoff for the limiting amplifier
Figure 5. Single-Ended Input Termination
inputs. DC levels at these inputs disrupt the offset-
correction loop.
to the ADI- input to minimize common-mode coupling
problems.
is determined by either C
impedance or C
and R
T
0.22μF
= 50Ω, the low-frequency cutoff is 29kHz.
C
b
Applications Information
Driving the Limiting Amplifier
b
R
50Ω
C
0.22μF
/2 together with R
T
b
5.6nF
C
IN
T
(50Ω) must be referenced
IN
ADI+
ADI-
and the 2.5kΩ input
T
. With C
2.5kΩ
Single-Ended
MAX3676
b
= 0.22μF
CC
as