MT8JSF25664HDZ-1G1D1 Micron Technology Inc, MT8JSF25664HDZ-1G1D1 Datasheet - Page 9

• Manufacturer Part Number: MT8JSF25664HDZ-1G1D1
• Manufacturer: Micron Technology Inc

Specifications of MT8JSF25664HDZ-1G1D1

• Main Category: DRAM Module
• Sub-category: DDR3 SDRAM
• Module Type: 204SODIMM
• Device Core Size: 64b
• Organization: 256Mx64
• Total Density: 2GByte
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Number Of Elements: 8
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 204
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

General Description
Fly-By Topology
09005aef83ccf92a
jsf8c128_256x64hdz.pdf – Rev. A 10/09 EN
DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod-
ules use DDR architecture to achieve high-speed operation. DDR3 architecture is
essentially an 8n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM
module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-
fers at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, com-
mand, and address buses have been routed in a fly-by topology, where each clock,
control, command, and address pin on each DRAM is connected to a single trace and
terminated (rather than a tree structure, where the termination is off the module near
the connector). Inherent to fly-by topology, the timing skew between the clock and DQS
signals can be easily accounted for by using the write-leveling feature of DDR3.
1GB, 2GB (x64, DR) 204-Pin DDR3 SDRAM SODIMM
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
General Description
©2009 Micron Technology, Inc. All rights reserved.