TC59SM816BFTL-80 Toshiba, TC59SM816BFTL-80 Datasheet - Page 8

• Manufacturer Part Number: TC59SM816BFTL-80
• Manufacturer: Toshiba

Specifications of TC59SM816BFTL-80

• Lead Free Status / RoHS Status: Not Compliant

(10)
CKE to clock disable (CKE Latency)
DQM to output in High-Z (Read DQM Latency)
DQM to input data delay (Write DQM Latency)
Write command to input data (Write Data Latency)
Precharge to DQ Hi-Z Lead time
Precharge to Last Valid data out
Burst Stop Command to DQ Hi-Z Lead time
Burst Stop Command to Last Valid data out
Read with Autoprecharge Command to Active/Ref Command
Write with Autoprecharge Command to Active/Ref Command
CS to Command input ( CS Latency)
(8)
(9)
These parameters account for the number of clock cycles and depend on the operating frequency of the
Power-up Sequence
clock, as follows:
Power-up must be performed in the following sequence.
The Mode Register Set command can be invoked either before or after the Auto Refresh dummy cycles.
AC Latency Characteristics
1)
2)
3)
4)
5)
the number of clock cycles = specified value of timing / clock period
(count fractions as a whole number)
Power must be applied to V
“NOP” state. The CLK signals must be started at the same time.
After power-up a pause of at least 200 µs is required. It is required that DQM and CKE signals
must be held “High” (V
All banks must be precharged.
The Mode Register Set command must be asserted to initialize the Mode Register.
A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of
the device.
CC
levels) to ensure that the DQ output is in High-impedance state.
CC
and V
CCQ
TC59SM816/08/04BFT/BFTL-70,-75,-80
(simultaneously) while all input signals are held in the
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
2001-06-11 8/49
BL + t
BL + t
BL + t
BL + t
1
2
0
0
0
2
3
1
2
2
3
1
2
RP
RP
RP
RP
Cycle + ns
Cycle