TC59SM816BFTL-80 Toshiba, TC59SM816BFTL-80 Datasheet
TC59SM816BFTL-80
Specifications of TC59SM816BFTL-80
Related parts for TC59SM816BFTL-80
TC59SM816BFTL-80 Summary of contents
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... It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. ...
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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. ...
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BLOCK DIAGRAM CLK CLOCK BUFFER CKE CONTROL CS SIGNAL COMMAND RAS GENERATOR DECODER CAS WE A10 MODE REGISTER ADDRESS BUFFER A0~A9 A11, A12 BS0 BS1 REFRESH COLUMN COUNTER COUNTER NOTE: The TC59SM804BFT/BFTL configuration is 8192 × 2048 × ...
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ABSOLUTE MAXIMUM RATINGS SYMBOL Input, Output Voltage IN OUT Power Supply Voltage CC CCQ T Operating Temperature opr T Storage Temperature stg T Soldering Temperature (10s) solder P Power Dissipation D I Short-Circuit Output ...
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DC CHARACTERISTICS (V PARAMETER OPERATING CURRENT = min min Active Precharge command cycling without burst operation STANDBY CURRENT = min (min (max), IH/L ...
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AC CHARACTERISTICS AND OPERATING CONDITIONS = = = = 3.3 V ± ± ± ± 0 0°~70°C) (Notes SYMBOL PARAMETER t Ref/Active to Ref/Active Command Period RC t Active ...
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NOTES: (1) Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device. (2) All voltages are referenced to V (3) These parameters depend on the cycle rate and these values are measured at a ...
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These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number) ...
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TIMING DIAGRAMS Command Input Timing V IH CLK RAS CAS WE A0~A12 BS0, BS1 t CKS CKE TC59SM816/08/04BFT/BFTL-70,-75,- CMS CMH t t CMS CMH t t CMS CMH t t CMS CMH t ...
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Read Timing CLK CS RAS CAS WE A0~A12 BS0, BS1 DQ Read command TC59SM816/08/04BFT/BFTL-70,-75,-80 Read CAS latency Output Output data valid data valid Burst length 2001-06-11 10/49 ...
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Control Timing of Input Data (TC59SM808/M804) (Word Mask) CLK t CMH DQM DQ0~DQ7 Input data valid (DQ0~DQ3)* (Clock Mask) CLK t CKH CKE DQ0~DQ7 Input data valid (DQ0~DQ3)* Control Timing of Output ...
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Control Timing of Input Data (TC59SM816) (Word Mask) CLK t CMH LDQM UDQM Input DQ0~DQ7 data valid Input DQ8~DQ15 data valid (Clock Mask) CLK t CKH CKE Input ...
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Control Timing of Output Data (TC59SM816) (Output Enable) CLK t CMH LDQM UDQM DQ0~DQ7 DQ8~DQ15 (Clock Mask) CLK t CKH CKE DQ0~DQ7 DQ8~DQ15 TC59SM816/08/04BFT/BFTL-70,-75,-80 ...
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Mode Register Set Cycle CLK t t CMS CMH CMS CMH RAS t t CMS CMH CAS t t CMS CMH A0~A12 Set Register BS0, BS1 data A0 Burst Length A1 A2 ...
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OPERATING TIMING EXAMPLE Figure 1. Interleaved Bank Read (Burst Length = CLK CS RAS t RAS CAS WE BS0 BS1 t RCD A10 RAa A0~A9, RAa CAw A11, A12 DQM CKE DQ t RRD ...
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Figure 2. Interleaved Bank Read (Burst Length = CLK CS RAS t RAS CAS WE BS0 BS1 t RCD A10 RAa RBb A0~A9, RAa CAw RBb A11, A12 DQM CKE DQ t RRD Bank#0 ...
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Figure 3. Interleaved Bank Read (Burst Length = CLK CS RAS CAS WE BS0 BS1 t RCD A10 RAa A0~A9, RAa CAx A11, A12 DQM CKE DQ t RRD Bank#0 Active Read Bank#1 Precharge ...
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Figure 4. Interleaved Bank Read (Burst Length = CLK CS RAS CAS WE BS0 BS1 t RCD A10 RAa A0~A9, RAa CAx A11, A12 DQM CKE DQ t RRD Bank#0 Active Read Bank#1 Bank#2 ...
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Figure 5. Interleaved Bank Write (Burst Length = CLK CS RAS CAS t RCD WE BS0 BS1 A10 RAa A0~A9, RAa CAx A11, A12 DQM CKE DQ ax0 ax1 t RRD Bank#0 Active Write ...
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Figure 6. Interleaved Bank Write (Burst Length = 8, Auto Precharge CLK CS RAS CAS WE BS0 BS1 t RCD A10 RAa A0~A9, RAa CAx A11, A12 DQM CKE DQ ax0 ax1 t RRD Bank#0 ...
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Figure 7. Page Mode Read (Burst Length = CLK CS RAS CAS WE BS0 BS1 t RCD A10 RAa RBb A0~A9, RAa CAl RBb A11, A12 DQM CKE DQ t RRD Bank#0 Active Read ...
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Figure 8. Page Mode Read/Write (Burst Length = CLK CS RAS CAS WE BS0 BS1 t RCD RAa A10 A0~A9, RAa CAx A11, A12 DQM CKE DQ Bank#0 Active Read Bank#1 Bank#2 Idle Bank#3 ...
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Figure 9. Auto Precharge Read (Burst Length = CLK CS RAS t RAS CAS WE BS0 BS1 t RCD RAa A10 A0~A9, RAa CAw A11, A12 DQM CKE DQ Bank#0 Active Read Bank#1 Bank#2 ...
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Figure 10. Auto Precharge Write (Burst Length = CLK CS RAS t RAS CAS WE BS0 BS1 t RCD RAa A10 A0~A9, RAa CAw A11, A12 DQM CKE DQ aw0 aw1 aw2 aw3 Bank#0 ...
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Figure 11. Auto Refresh Cycle CLK RAS CAS WE BS0, BS1 A10 A0~A9, A11, A12 DQM CKE DQ All Banks Precharge Auto Refresh TC59SM816/08/04BFT/BFTL-70,-75,- ...
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Figure 12. Self Refresh Cycle CLK RAS CAS WE BS0, BS1 A10 A0~A9, A11, A12 DQM CKE t CKS DQ All Banks Precharge Self Refresh Entry TC59SM816/08/04BFT/BFTL-70,-75,- ...
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Figure 13. Power Down Mode CLK CS RAS CAS WE BS RAa A10 A0~A9, RAa A11, A12 DQM t SB CKE t CKS DQ Active NOP Power Down Mode Entry Power Down Mode Exit Note): ...
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Figure 14. Burst Read and Single Write (Burst Length = CLK CS RAS CAS t RCD WE BS0 BS1 RBa A10 A0~A9, RBa CBv A11, A12 DQM CKE DQ Bank#0 Bank#1 Active Read Bank#2 ...
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... PIN FUNCTIONS CLOCK INPUT: CLK The CLK input is used as the reference for SDRAM operations. Operations are synchronized to the positive edges of CLK. CLOCK ENABLE: CKE The CKE input is used to suspend the internal CLK. When the CKE signal is asserted “low”, the internal CLK is suspended and output data is held intact while CKE is asserted “ ...
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CHIP SELECT: CS The CS input controls the latching of the commands on the positive edges of CLK when CS is asserted “low”. No commands are latched as long held “high”. RAS ROW ADDRESS STROBE: The RAS ...
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Operation Mode Table 1 shows the truth table for the operation commands. Table 1. Truth Table (Note (1) and (2) ) Command Device State Bank Activate Idle Bank Precharge Precharge All Write Active Write with Auto Precharge Active Read Active ...
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Command Function 1-1 Bank Activate command ( RAS = L, CAS = BS0, BS1 = Bank, A0~A12 = Row Address) The Bank Activate command activates the bank designated by the BS (Bank Select) signal. Row ...
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... The Refresh operation must be performed 8192 times within 64 ms. The next command can be issued after t from the end of the Auto Refresh command. When the Auto Refresh command is issued, All RC banks must be in the idle state. The Auto Refresh operation is equivalent to the CAS -before- RAS operation in a conventional DRAM. TC59SM816/08/04BFT/BFTL-70,-75,-80 2001-06-11 33/49 ...
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Self Refresh Entry command ( RAS = L, CAS = CKE = L, BS0, BS1, A0~A12 = Don’t care) The Self Refresh Entry command is used to enter Self Refresh mode. While the device is ...
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Read Operation Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after t from the Bank Activate command, the data is read out sequentially, synchronized to the ...
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Precharge There are two commands which perform the Precharge operation: Bank Precharge and Precharge All. When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank ...
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Mode Register Operation The Mode register designates the operation mode for the Read or Write cycle. This register is divided into three fields; A Burst Length field to set the length of burst data, an Addressing Mode selected bits ...
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Addressing sequence of Sequential mode A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length as shown in Table 2. Table 2. Addressing sequence for Sequential mode ...
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Addressing sequence example (Burst Length = 8 and input address is 13.) DATA A8 A7 Data0 0 0 Data1 0 0 Data2 0 0 Data3 0 0 Data4 0 0 Data5 0 0 Data6 0 0 Data7 0 0 Read ...
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... Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before- RAS refresh of conventional DRAMs and is performed by issuing the Auto Refresh command while all banks are in the idle state. By repeating the Auto Refresh cycle, all banks refreshed automatically ...
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Figure 15. Auto Precharge timing (Read cycle) 0 (1) CAS Latency = 2 (a) Burst Length = 1 Command Read DQ (b) Burst Length = 2 Command Read DQ (c) Burst Length = 4 Command Read DQ (d) Burst Length ...
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Figure 16. Auto Precharge timing (Write cycle) 0 (1) CAS Latency = 2 (a) Burst Length = 1 Command Write DQ D0 (b) Burst Length = 2 Command Write DQ D0 (c) Burst Length = 4 Command Write DQ D0 ...
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Figure 17. Timing chart for Read-to-Write cycle In the case of Burst Length = 4 (1) CAS Latency = 2 (a) Command DQM DQ (b) Command DQM DQ (2) CAS Latency = 3 (a) Command DQM DQ (b) Command DQM ...
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Figure 18. Timing chart for Write-to-Read cycle In the case of Burst Length = 4 (1) CAS Latency = 2 (a) Command DQM DQ (b) Command DQM DQ (2) CAS Latency = 3 (a) Command DQM DQ (b) Command DQM ...
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Figure 19. Timing chart for Burst Stop cycle (Burst stop command) 0 (1) Read Cycle Latency = 2 (a) CAS Command Read DQ Latency = 3 (b) CAS Command Read DQ (2) Write Cycle Command Write DQ D0 • Note) ...
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Figure 20. Timing chart for Burst Stop cycle (Precharge command) In the case of Burst Length = 8 (1) Read Cycle Latency = 2 (a) CAS Read Command DQ Latency = 3 (b) CAS Command Read DQ (2) Write Cycle ...
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Figure 21 (a). CKE/DQM Input timing (Write cycle) CLK Cycle No. 1 External CLK Internal CKE DQM CLK Cycle No. 1 External CLK Internal CKE DQM CLK Cycle No. 1 External CLK Internal CKE ...
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Figure 21 (b). CKE/DQM Input timing (Read cycle) CLK Cycle No. 1 External CLK Internal CKE DQM CLK Cycle No. 1 External CLK Internal CKE DQM CLK Cycle No. 1 External CLK Internal CKE ...
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PACKAGE DIMENSIONS TC59SM816/08/04BFT/BFTL-70,-75,-80 Unit: mm 2001-06-11 49/49 ...