TC59SM816BFTL-80 Toshiba, TC59SM816BFTL-80 Datasheet - Page 29

• Manufacturer Part Number: TC59SM816BFTL-80
• Manufacturer: Toshiba

Specifications of TC59SM816BFTL-80

• Lead Free Status / RoHS Status: Not Compliant

PIN FUNCTIONS
CLOCK INPUT: CLK
edges of CLK.
CLOCK ENABLE: CKE
CLK is suspended and output data is held intact while CKE is asserted “low”. When the device is not running a
Burst cycle, the CKE input controls the entry to the Power Down and Self Refresh modes. When the Self
Refresh command is issued, the device must be in the idle state.
BANK SELECT: BS0, BS1
four-bank memory cell arrays. The BS0, BS1 inputs are latched at the time of assertion of the operation
commands and selects the bank to be used for the operation.
ADDRESS INPUTS: A0~A12
Read or Write command. Also, the A0~A12 inputs are used to set the data in the Mode register in a Mode
Register Set cycle.
The CLK input is used as the reference for SDRAM operations. Operations are synchronized to the positive
The CKE input is used to suspend the internal CLK. When the CKE signal is asserted “low”, the internal
The TC59SM816BFT/BFTL, TC59SM808BFT/BFTL and the TC59SM804BFT/BFTL are organized as
The A0~A12 inputs are address to access the memory cell array, as following table.
The row address bits are latched at the Bank Activate command and column address bits are latched on the
TC59SM816BFT/BFTL
TC59SM808BFT/BFTL
TC59SM804BFT/BFTL
BS0
0
1
0
1
BS1
0
0
1
1
Row Address
A0~A12
A0~A12
A0~A12
Bank#0
Bank#1
Bank#2
Bank#3
Column Address
A0~A9, A11
TC59SM816/08/04BFT/BFTL-70,-75,-80
A0~A8
A0~A9
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