CP3BT26G18NEPX/NOPB National Semiconductor, CP3BT26G18NEPX/NOPB Datasheet - Page 79

• Manufacturer Part Number: CP3BT26G18NEPX/NOPB
• Manufacturer: National Semiconductor

Specifications of CP3BT26G18NEPX/NOPB

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: LQFP
• Lead Free Status / RoHS Status: Compliant

15.5
The Bluetooth controller is capable of putting itself into a
sleep mode for a specified number of Slow Clock cycles. In
this mode, the controller clocks are stopped internally. The
only circuitry which remains active are two counters
(counter N and counter M) running at the Slow Clock rate.
These counters determine the duration of the sleep mode.
The sequence of events when entering the LLC sleep mode
is as follows:
1. The current Bluetooth counter contents are read by the
2. Software “estimates” the Bluetooth counter value after
3. The new Bluetooth counter value is written into the
4. The Bluetooth sequencer RAM is updated with the
5. The Bluetooth sequencer RAM and the Bluetooth LLC
6. Hardware Clock Control (HCC) is enabled, and the
7. The Bluetooth sequencer checks if HCC is enabled. If
8. The M-counter starts counting. After M + 1 Slow Clock
9. The PMM restarts the 12 MHz Main Clock (and the
CPU.
leaving the sleep mode.
Bluetooth counter register.
code required by the Bluetooth sequencer to enter/exit
Sleep mode.
registers are switched from the System Clock domain
to the local 12 MHz Bluetooth clock domain. At this
point, the Bluetooth sequencer RAM and Bluetooth
LLC registers cannot be updated by the CPU, because
the CPU no longer has access to the Bluetooth LLC.
CP3BT26 enters a power-saving mode (Power Save or
Idle mode). While in Power Save mode, the Slow Clock
is used as the System Clock. While in Idle mode, the
System Clock is turned off.
HCC is enabled, the sequencer asserts HCC to the
PMM. On the next rising edge of the low-frequency
clock, the 1MHz clock and the 12 MHz clock are
stopped locally within the Bluetooth LLC. At this point,
the Bluetooth sequencer is stopped.
cycles, the HCC signal to the PMM is deasserted.
PLL, if required). The N-counter starts counting. After
N + 1 Slow Clock cycles, the Bluetooth clocks (1 MHz
Figure 25. LMX5252 Power-Up Sequence
BLUETOOTH SLEEP MODE
79
10. The Bluetooth sequencer waits for the completion of
11. The PMM switches the System Clock to the high-fre-
15.6
Table 32 shows the memory map of the Bluetooth LLC glo-
bal registers.
15.7
The sequencer RAM is a 1K memory-mapped section of
RAM that contains the sequencer program. This RAM can
be read and written by the CPU in the same way as the Stat-
ic RAM space and can also be read by the sequencer in the
Bluetooth LLC. Arbitration between these devices is per-
formed in hardware.
Table 32 Memory Map of Bluetooth Global Registers
1 MHz/12 MHz
BT LCC Clock
System Clock
(offset from 0E F180h)
and 12 MHz) are turned on again. The Bluetooth se-
quencer starts operating.
the sleep mode. When completed, the Bluetooth se-
quencer asserts a wake-up signal to the MIWU (see
Section 13.0).
quency clock and the CP3BT26 enters Active mode
again. HCC is disabled. The Bluetooth sequencer RAM
and Bluetooth LLC registers are switched back from the
local 12 MHz Bluetooth clock to the System Clock. At
this point, the Bluetooth sequencer RAM and Bluetooth
LLC registers are once again accessible by the CPU. If
enabled, an interrupt is issued to the CPU.
Main Clock
Sequencer
Figure 26. Bluetooth Sleep Mode Sequence
BT Clock
12 MHz
0000h
0049h
CPU
HCC
HCC
BLUETOOTH GLOBAL REGISTERS
BLUETOOTH SEQUENCER RAM
Address
Stopped/Slow
System Clock
Power Save
Deasserted
–
Main Clock
–
0048h
007Fh
Asserted
Disabled
Stopped
Stopped
Stopped
Enabled
Sleep Mode
Prepare for
Active
Active
Active
Active
Active
CPU
Global LLC Configuration
N
Start-up
Description
M
Unused
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CPU Handles
Wake-Up IRQ
from MIWU
DS017