CP3BT26G18NEPX/NOPB National Semiconductor, CP3BT26G18NEPX/NOPB Datasheet - Page 65

• Manufacturer Part Number: CP3BT26G18NEPX/NOPB
• Manufacturer: National Semiconductor

Specifications of CP3BT26G18NEPX/NOPB

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: LQFP
• Lead Free Status / RoHS Status: Compliant

13.1.1
The WK0EDG register is a word-wide read/write register
that controls the edge sensitivity of the MIWU channels. The
WK0EDG register is cleared upon reset, which configures
all channels to be triggered on rising edges. The register for-
mat is shown below.
WKED
13.1.2
The WK1EDG register is a word-wide read/write register
that controls the edge sensitivity of the MIWU channels. The
WK1EDG register is cleared upon reset, which configures
all channels to be triggered on rising edges. The register for-
mat is shown below.
WKED
13.1.3
The WK0ENA register is a word-wide read/write register
that individually enables or disables wake-up events from
the MIWU channels. The WK0ENA register is cleared upon
reset, which disables all wake-up/interrupt channels. The
register format is shown below.
WKEN
15
15
15
Wake-Up Edge Detection Register (WK0EDG)
Wake-Up 1 Edge Detection Register (WK1EDG)
Wake-Up Enable Register (WK0ENA)
The Wake-Up Edge Detection bits control the
edge sensitivity for MIWU channels. The
WKED15:0 bits correspond to the WUI15:0
channels, respectively.
0
1
The Wake-Up Edge Detection bits control the
edge sensitivity for MIWU channels. The
WKED15:0 bits correspond to the WUI31:16
channels, respectively.
0
1
The Wake-Up Enable bits enable and disable
the MIWU channels. The WKEN15:0 bits cor-
respond to the WUI15:0 channels, respective-
ly.
0
1
–
–
–
–
–
–
Triggered on rising edge (low-to-high
transition).
Triggered on falling edge (high-to-low
transition).
Triggered on rising edge (low-to-high
transition).
Triggered on falling edge (high-to-low
transition).
MIWU channel wake-up events disabled.
MIWU channel wake-up events enabled.
WKED
WKED
WKEN
0
0
0
65
13.1.4
The WK1ENA register is a word-wide read/write register
that individually enables or disables wake-up events from
the MIWU channels. The WK1ENA register is cleared upon
reset, which disables all wake-up/interrupt channels. The
register format is shown below.
WKEN
13.1.5
The WK0IENA register is a word-wide read/write register
that enables and disables interrupts from the MIWU chan-
nels. The register format is shown below.
WKIEN
13.1.6
The WK1IENA register is a word-wide read/write register
that enables and disables interrupts from the MIWU chan-
nels. The register format is shown below.
WK1IEN
15
15
15
Wake-Up Interrupt Enable Register (WK0IENA)
Wake-Up 1 Interrupt Enable Register
Wake-Up 1 Enable Register (WK1ENA)
(WK1IENA)
The Wake-Up Enable bits enable and disable
the MIWU channels. The WKEN15:0 bits cor-
respond to the WUI31:16 channels, respec-
tively.
0
1
The Wake-Up Interrupt Enable bits control
whether MIWU channels generate interrupts.
The WKIEN15:0 bits correspond to the
WUI15:0 channels, respectively.
0
1
The Wake-Up Interrupt Enable bits control
whether MIWU channels generate interrupts.
The WKIEN15:0 bits correspond to the
WUI31:16 channels, respectively.
0
1
–
–
–
–
–
–
MIWU channel wake-up events disabled.
MIWU channel wake-up events enabled.
Interrupt disabled.
Interrupt enabled.
Interrupt disabled.
Interrupt enabled.
WKIEN
WKIEN
WKEN
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