CP3BT26G18NEPX/NOPB National Semiconductor, CP3BT26G18NEPX/NOPB Datasheet - Page 43

• Manufacturer Part Number: CP3BT26G18NEPX/NOPB
• Manufacturer: National Semiconductor

Specifications of CP3BT26G18NEPX/NOPB

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: LQFP
• Lead Free Status / RoHS Status: Compliant

If the DMASTAT.VLD bit is clear:
The DMACNTLn.CHEN bit must be cleared before loading
the DMACNTLn register to avoid prematurely starting a new
DMA transfer.
Note: The ADCBn and ADRBn registers are used only in
indirect (memory-to-memory ) transfer. In direct (flyby)
mode, the DMAC does not use them and therefore does not
copy ADRBn into ADCBn.
9.3.3
This mode allows the DMAC to continuously fill the same
memory area without software intervention.
Initialization
Continuation
When the BLTCn counter reaches 0:
If the DMASTAT.TC bit is set:
If the DMASTAT.TC bit is clear:
Termination
The
DMACNTLn.CHEN bit is cleared.
9.4
In addition to the hardware requests from I/O devices, a
DMA transfer request can also be initiated by software. A
software DMA transfer request must be used for block copy-
ing between memory devices.
When the DMACNTLn.SWRQ bit is set, the corresponding
DMA channel receives a DMA transfer request. When the
DMACNTLn.SWRQ bit is clear, the software DMA transfer
request of the corresponding channel is inactive.
1. The transfer operation terminates.
2. The channel sets the DMASTAT.OVR bit.
3. The DMASTAT.CHAC bit is cleared.
4. An
1. Write the block addresses and byte count into the AD-
2. Set the DMACNTLn.OT bit to select auto-initialize
3. Set the DMACNTLn.CHEN bit to activate the channel
1. The contents of the ADRAn, ADRBn, and BLTRn regis-
2. The DMAC channel checks the value of the DMAS-
1. The DMASTAT.OVR bit is set.
2. A level interrupt is generated if enabled by the
3. The operation is repeated.
1. The DMASTAT.TC bit is set.
2. A level interrupt is generated if enabled by the
3. The DMAC operation is repeated.
DMACNTLn.EOVR bit.
CAn, ADCBn, and BLTCn counters, as well as the
ADRAn, ADRBn, and BLTRn registers.
mode.
and enable it to respond to DMA transfer requests.
ters are copied to the ADCAn, ADCBn, and BLTCn
counters.
TAT.TC bit.
DMACNTLn.EOVR bit.
DMACNTLn.ETC bit.
DMA
Auto-Initialize Operation
SOFTWARE DMA REQUEST
interrupt
transfer
is
generated
is
terminated
if
enabled
when
by
the
the
43
For each channel, use the software DMA transfer request
only when the corresponding hardware DMA request is in-
active and no terminal count interrupt is pending. Software
can poll the DMASTAT.CHAC bit to determine whether the
DMA channel is already active. After verifying the DMAS-
TATn.CHAC bit is clear (channel inactive), check the DMAS-
TATn.TC (terminal count) bit. If the TC bit is clear, then no
terminal count condition exists and therefore no terminal
count interrupt is pending. If the channel is not active and no
terminal count interrupt is pending, software may request a
DMA transfer.
9.5
When the FREEZE signal is active, all DMA operations are
stopped. They will start again when the FREEZE signal
goes inactive. This allows breakpoints to be used in debug
systems.
9.6
There are four identical sets of DMA controller registers, as
listed in Table 18.
DMACNTL0
DMACNTL1
DMASTAT0
DMASTAT1
ADCA0
ADRA0
ADCB0
ADRB0
ADCA1
ADRA1
ADCB1
ADRB1
BLTC0
BLTR0
BLTC1
BLTR1
Name
DEBUG MODE
DMA CONTROLLER REGISTER SET
Table 18 DMA Controller Registers
FF F81Ch
FF F83Ch
FF F80Ch
FF F81Eh
FF F82Ch
FF F83Eh
FF F800h
FF F804h
FF F808h
FF F810h
FF F814h
FF F820h
FF F824h
FF F828h
FF F830h
FF F834h
Address
Block Length Register
DMA Control Register
Block Length Register
DMA Control Register
DMA Status Register
DMA Status Register
Device A Address
Device A Address
Device B Address
Device B Address
Device A Address
Device A Address
Device B Address
Device B Address
Counter Register
Counter Register
Counter Register
Counter Register
Counter Register
Counter Register
Block Length
Block Length
Description
Register
Register
Register
Register
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