CP3BT26G18NEPX/NOPB National Semiconductor, CP3BT26G18NEPX/NOPB Datasheet - Page 77
CP3BT26G18NEPX/NOPB
Manufacturer Part Number
CP3BT26G18NEPX/NOPB
Description
Manufacturer
National Semiconductor
Datasheet
1.CP3BT26G18NEPXNOPB.pdf
(280 pages)
Specifications of CP3BT26G18NEPX/NOPB
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Package Type
LQFP
Lead Free Status / RoHS Status
Compliant
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An example of a 32-bit write is shown in Table 31. In this ex-
ample, the 32-bit value FFFF DC04h is written to register
address 0Ah. In cycle 1, the high word (FFFFh) is written. In
the first part of cycle 2, the CP3BT26 drives the header, R/
W bit, and register address for a read cycle. In the second
part of cycle 2, the LMX5252 drives the counter value. The
Cycle
1
2
3
4
101 0 01010 1111111111111111
101 1 01010
101 0 01010 1101110000000100
101 1 01010
Serial Data on SDAT
0000000000000000
0000000000000001
Table 31 Example of 32-Bit Write with Interleaved Reads
Figure 21. 32-Bit Write Timing
Figure 22. 32-Bit Read Timing
Write cycle driven by CP3BT26. Data is FFFFh. Address is 0Ah.
First part of read cycle driven by CP3BT26. Address is 0Ah.
Second part of read cycle driven by LMX5252. Counter value is 0.
Write cycle driven by CP3BT26. Data is DC04h. Address is 0Ah.
First part of read cycle driven by CP3BT26. Address is 0Ah.
Second part of read cycle driven by LMX5252. Counter value is 1.
77
counter value is 0, which indicates one word has been writ-
ten. In cycle 3, the low word (DC04h) is written. In the first
part of cycle 4, the CP3BT26 drives the header, R/W bit,
and register address for a read cycle. In the second part of
cycle 4, the LMX5252 drives the counter value. The counter
value is 1, which indicates two words have been written.
Description
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