MC9328MX21SVM Freescale, MC9328MX21SVM Datasheet - Page 34

• Manufacturer Part Number: MC9328MX21SVM
• Manufacturer: Freescale

Specifications of MC9328MX21SVM

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Specifications
3.12
3.12.1
Figure
signals of the NFC at module level, and
(NFC) timing parameters are based on the internal NFC clock generated by the Clock Controller module,
where time T is the period of the NFC clock in ns. Per the i.MX21S Reference Manual, specifically the
Phase-Locked (PLL), Clock, and Reset Controller chapter, the NFC clock is derived from the same clock
which drives the CPU clock (FCLK) that is fed through the NFCDIV block to generate the NFC clock.
The relationship between the NFC clock and the external timing parameters of the NFC is provided in
Table
Table 24
22.17 MHz and 33.25 MHz. For example, assuming a 266 MHz FCLK (CPU clock), NFCDIV should be
set to divide-by-12 to generate a 22.17 MHz NFC clock and divide-by-8 to generate a 33.25 MHz NFC
clock. The user should compare the parameters of the selected NAND Flash memory with the NFC
external timing parameters to determine the proper NFC clock. The maximum NFC clock allowed is
66 MHz. It should also be noted that the default NFC clock on power up is 16.63 MHz.
34
24.
25,
also provides two examples of external timing parameters with NFC clock frequencies of
External Memory Interface (EMI) Electricals
Figure
NAND-Flash Controller (NFC) Interface
26,
NFIO[7:0]
NFALE
NFWE
Figure
NFCLE
NFCE
Figure 25. Command Latch Cycle Timing DIagram
27, and
MC9328MX21S Technical Data, Rev. 1.3
NF6
NF1
NF3
Figure 28
Table 24
NF8
depict the relative timing requirements among different
NF5
lists the timing parameters. The NAND Flash Controller
command
NF4
NF9
NF2
NF7
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