ZPSD511B1C15J STMicroelectronics, ZPSD511B1C15J Datasheet - Page 87

• Manufacturer Part Number: ZPSD511B1C15J
• Manufacturer: STMicroelectronics

Specifications of ZPSD511B1C15J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Counter/Timer
Registers
(Cont.)
84
PSD5XX Family
Mode Select Bit (0):
Increment/Decrement Bit (1): This bit is used to set the Counter/Timer in increment or
Select Counter Bit (2):
After a Counter/Timer is started by the Global Command Register, it can be re-configured by
changing the individual Command Register. The steps to re-configure a Counter/Timer are:
1. Disable the Counter/Timer by writing a “0” to the Select Counter Bit (bit 2) of the
2. Change the Counter/Timer configuration by writing the new value (bit 2 remains at “0”)
3. Enable the Counter/Timer again by writing the new value with bit 2 set to “1” to the
9.6.2.2 Command Registers for Counter/Timers CMD0, CMD1, CMD2, CMD3:
Each of the Counter/Timer units (CTU) has one Command Register associated with it.
A description of these various CTU command bits is provided below. Refer to CSIOP
Tables 23 and 24 for their addresses and selection details. Figure 43 describes the
Command Register bits.
The following is the description of Counter/Timer0 CMD0 register bits. Bits in CMD1, CMD2
and CMD3 have similar descriptions. Refer to Figure 43 also.
NOTES: 1. At RESET these bits come up as 0s.
Enable/
Disable
Using
Pin,
PPLD
Macrocell
or
Software
Command Register.
to the Command Register.
Command Register.
Bit 7
2. In WatchDog Mode, CMD2 register bits are Don’t Cares.
Software
Gating
Bit for
Load /
Store cmd
Using Pin
or PPLD
Macrocell
Bit 6
Pin /
PPLD
Macrocell
Bit 5
This bit selects the Counter/Timer0 operation mode. After
RESET Counter/Timer0 initializes in waveform/event count
mode. When this bit is set to
1: The Counter/Timer0 operates in Pulse/Time capture
0: The Counter/Timer0 operates in Waveform/Event count
NOTE: See Table 24 for details of Timer mode set up.
decrement mode. The RESET state is Decrement mode.
When this bit is set to
1: The Counter/Timer0 is in increment mode.
0: The Counter/Timer0 is in decrement mode.
NOTE: In WatchDog mode Counter #2 is in decrement
This bit is used to select or deselect Counter/Timer0.
At RESET this bit initializes as 0 which means
Counter/Timer0 is deselected. When this bit is set to
1: Counter/Timer0 is selected (counting enabled).
0: Counter/Timer0 is deselected (counting disabled).
modes.
modes.
Input
Polarity
Bit 4
mode only.
Output
Polarity
Bit 3
Select
Counter
Bit 2
Increment /
Decrement
Bit 1
Mode
Select
Bit 0