ZPSD511B1C15J STMicroelectronics, ZPSD511B1C15J Datasheet - Page 106

• Manufacturer Part Number: ZPSD511B1C15J
• Manufacturer: STMicroelectronics

Specifications of ZPSD511B1C15J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

10.0
Page
Register
11.0
Security
Protection
Figure 49. Page Register
The Page Register is 4 bits wide and consists of four D flip flops.The outputs of the Register
(PGR0 – PGR3) are connected to the input bus of the ZPLD. By including the four outputs
as inputs to the DPLD, the addressing capability of the microcontroller is increased by a
factor of 16.
Figure 49 shows the Page Register block diagram. Inputs to the four flip flops are connected
to data bus D0-D3. The output of the Register can be read by the microcontroller. The
Register can operate as an independent register to the microcontroller if page mode is not
implemented.
The PSD5XX has a programmable security bit which offers protection from unauthorized
duplication. When the security bit is set, the contents of the EPROM, the PSD5XX
non-volatile configuration bits and ZPLD data are prevented from being read by EPROM
programmers.
The security bit is set through the PSDsoft Software and is embedded in the compiled
output file. The security bit is UV erasable and a secured part can be erased and then
re-programmed.
RESET
D0 – D3
R/W
D0
D1
D2
D3
REGISTER
PAGE
Q0
Q1
Q2
Q3
PGR0
PGR1
PGR2
PGR3
ZPLD
DPLD
GPLD
PPLD
ES0 – 3
RS0
PSD5XX Family
103