PLRXPL-VI-S24-22 JDS UNIPHASE, PLRXPL-VI-S24-22 Datasheet - Page 3

• Manufacturer Part Number: PLRXPL-VI-S24-22
• Manufacturer: JDS UNIPHASE

Specifications of PLRXPL-VI-S24-22

• Optical Fiber Type: TX/RX
• Optical Rise Time: 0.15/0.2ns
• Optical Fall Time: 0.15/0.2ns
• Operating Temperature Classification: Industrial
• Peak Wavelength: 850nm
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Lead Free Status / RoHS Status: Compliant

ROHS-COMPLIANT 2.125, 1.25 AND 1.063 GBPS 850 NM TRANSCEIVER
3
Section 1
Functional Description
PLRXPL-VI-S24-22 850 nm VCSEL Gigabit Transceiver is designed to transmit
and receive 8B/10B encoded serial optical data over 50/125 µm or 62.5/125 µm
multimode optical fi ber.
Transmitter
The transmitter converts 8B/10B encoded serial PECL or CML electrical data into
serial optical data meeting the requirements of 100-M5/M6-SN-I, 200-M5/M6-
SN-I Fibre Channel specifi cations and 1000BASE-SX Ethernet. Transmit data lines
(TD+ & TD-) are internally AC coupled with 100  differential termination.
An open collector compatible Transmit Disable (Tx_Dis) is provided. This pin is
internally terminated with a 10 k resistor to Vcc
. A logic “1,” or no connection
T
on this pin will disable the laser from transmitting. A logic “0” on this pin provides
normal operation.
The transmitter has an internal PIN monitor diode that is used to ensure constant
optical power output across supply voltage and temperature variations.
An open collector compatible Transmit Fault (TFault) is provided. The Transmit
Fault signal must be pulled high on the host board for proper operation. A logic
“1” output from this pin indicates that a transmitter fault has occurred, or the part
is not fully seated and the transmitter is disabled. A logic “0” on this pin indicates
normal operation.
Receiver
The receiver converts 8B/10B encoded serial optical data into serial PECL/CML
electrical data. Receive data lines (RD+ & RD-) are internally AC coupled with 100 
differential source impedance, and must be terminated with a 100  differential load.
The receiver’s bandwidth has been optimized for fully compliant operation at
2.125, 1.25 and 1.063 Gbps line rates without the use of rate select. Rate select pin
7 has no effect.
An open collector compatible Loss of Signal is provided. The LOS must be pulled
high on the host board for proper operation. A logic “0” indicates that light has
been detected at the input to the receiver (see Section 2.5 Optical characteristic,
Loss of Signal Assert/Deassert Time on page 9). A logic “1” output indicates that
insuffi cient light has been detected for proper operation.
Power supply fi ltering is recommended for both the transmitter and receiver. Fil-
tering should be placed on the host assembly as close to the Vcc pins as possible
for optimal performance.
Recommended “Application Schematics” are shown in Figure 2 on page 5.