CY7C4251-15JCT Cypress Semiconductor Corp, CY7C4251-15JCT Datasheet - Page 5

• Manufacturer Part Number: CY7C4251-15JCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4251-15JCT

• Configuration: Dual
• Density: 64Kb
• Access Time (max): 15ns
• Word Size: 9b
• Organization: 8Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PLCC
• Clock Freq (max): 40MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
The CY7C42X1 provides four status pins: Empty, Full, Almost
Empty, Almost Full. The Almost Empty/Almost Full flags are
programmable to single word granularity. The programmable
flags default to Empty – 7 and Full – 7.
The flags are synchronous - they change state relative to either
the Read clock (RCLK) or the Write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the flags
are updated exclusively by the RCLK. The flags denoting Almost
Full and Full states are updated exclusively by WCLK. The
synchronous flag architecture guarantees that the flags maintain
their status for at least one cycle.
All configurations are fabricated using advanced 0.65μ N-Well
CMOS technology. Input ESD protection is greater than 2001V,
and latch up is prevented by the use of guard rings.
Architecture
The CY7C42X1 consists of an array of 64 to 8K words of 9 bits
each (implemented by a dual-port array of SRAM cells), a read
pointer, a write pointer, control signals (RCLK, WCLK, REN1,
REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF).
Resetting the FIFO
During power up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs (Q
after the rising edge of RS. For the FIFO to reset to its default
state, a falling edge must occur on RS and the user must not read
or write while RS is LOW. All flags are guaranteed to be valid t
after RS is taken LOW.
FIFO Operation
When the WEN1 signal is active LOW and WEN2 is active HIGH,
data present on the D
rising edge of the WCLK signal. Similarly, when the REN1 and
REN2 signals are active LOW, data in the FIFO memory is
presented on the Q
rising edge of RCLK while REN1 and REN2 are active. REN1
and REN2 must set up t
function. WEN1 and WEN2 must occur t
to be a valid write function.
An output enable (OE) pin is provided to three-state the Q
outputs when OE is asserted. When OE is enabled (LOW), data
in the output register is available to the Q
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
Document #: 38-06016 Rev. *D
0–8
0–8
outputs. New data is presented on each
ENS
pins is written into the FIFO on each
before RCLK for it to be a valid read
ENS
0–8
before WCLK for it
outputs after t
0–8
) go LOW t
OE
RSF
RSF
0–8
.
maintains the data of the last valid read on its Q
after additional reads occur.
Write Enable 1 (WEN1). If the FIFO is configured for program-
mable flags, Write Enable 1 (WEN1) is the only write enable
control pin. In this configuration, when Write Enable 1 (WEN1) is
LOW, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every Write clock (WCLK).
Data is stored is the RAM array sequentially and independently
of any on-going read operation.
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags or
to have two write enables, which allows depth expansion. If Write
Enable 2/Load (WEN2/LD) is set active HIGH at Reset (RS =
LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every Write clock (WCLK).
Data is stored in the RAM array sequentially and independently
of any on-going read operation.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 8-bit offset registers
contained in the CY7C42X1 for writing or reading data to these
registers.
When the device is configured for programmable flags and both
WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH transition
of WCLK writes data from the data inputs to the empty offset least
significant bit (LSB) register. The second, third, and fourth
LOW-to-HIGH transitions of WCLK store data in the empty offset
most significant bit (MSB) register, full offset LSB register, and
full offset MSB register, respectively, when WEN2/LD and WEN1
are LOW. The fifth LOW-to-HIGH transition of WCLK while
WEN2/LD and WEN1 are LOW writes data to the empty LSB
register again.
values for the various device types.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read
and write operation. The next time WEN2/LD is brought LOW, a
write operation stores data in the next offset register in
sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2 are
LOW. LOW-to-HIGH transitions of RCLK Read register contents
to the data outputs. Writes and reads should not be preformed
simultaneously on the offset registers.
Figure 2
CY7C4421/4201/4211/4221
shows the registers sizes and default
CY7C4231/4241/4251
0–8
outputs even
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