CY7C4251-15JCT Cypress Semiconductor Corp, CY7C4251-15JCT Datasheet - Page 15

• Manufacturer Part Number: CY7C4251-15JCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4251-15JCT

• Configuration: Dual
• Density: 64Kb
• Access Time (max): 15ns
• Word Size: 9b
• Organization: 8Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PLCC
• Clock Freq (max): 40MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-06016 Rev. *D
Notes
24. If a write is performed on this rising edge of the write clock, there are Full – (m – 1) words of the FIFO when PAF goes LOW.
25. PAF offset = m.
26. 64-m words for CY7C4421, 256 – m words in FIFO for CY7C4201, 512 – m words for CY7C4211, 1024 – m words for CY7C4221, 2048 – m words for CY7C4231,
27. t
(if applicable)
WEN2/LD
4096 – m words for CY7C4241, 8192 – m words for CY7C4251.
RCLK and the rising edge of WCLK is less than t
SKEW2
WEN2
WCLK
WCLK
WEN1
D
WEN1
REN1,
RCLK
REN2
0
PAF
–D
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of
8
t
t
CLKH
CLKH
FULL − M+1 WORDS
t
CLK
t
t
ENS
ENS
t
IN FIFO
DS
PAE OFFSET
Figure 12. Programmable Almost Full Flag Timing
t
t
ENS
ENS
LSB
SKEW2
Figure 13. Write Programmable Registers
t
t
ENH
ENH
, then PAF may not change state until the next WCLK.
t
t
CLKL
CLKL
t
ENH
t
DH
Note
PAE OFFSET
25
Note
24
MSB
t
PAF
t
ENS
PAF OFFSET
t
SKEW2
FULL − M WORDS
LSB
IN FIFO
t
ENS
[27]
CY7C4421/4201/4211/4221
[26]
t
ENH
CY7C4231/4241/4251
PAF OFFSET
MSB
t
PAF
Page 15 of 20
[+] Feedback