CY7C4251-15JCT Cypress Semiconductor Corp, CY7C4251-15JCT Datasheet - Page 3

• Manufacturer Part Number: CY7C4251-15JCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4251-15JCT

• Configuration: Dual
• Density: 64Kb
• Access Time (max): 15ns
• Word Size: 9b
• Organization: 8Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PLCC
• Clock Freq (max): 40MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

Selection Guide
Pin Configuration
Table 1. Pin Definitions
Document #: 38-06016 Rev. *D
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Setup
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply Current
Density
D
Q
WEN1
WEN2/LD Dual
Mode Pin
REN1, REN2
WCLK
0–8
0–8
Pin
Data Inputs
Data Outputs
Write Enable 1
Write Enable 2
Load
Read Enable
Inputs
Write Clock
CY7C4421
Description
64 × 9
Name
REN1
RCLK
REN2
GND
PAE
PAF
OE
D
D
1
0
5
6
7
8
9
10
11
12
13
CY7C4201
Top View
4 3 2 1
14151617 181920
256 × 9
I/O
PLCC
Commercial
Industrial
O
I
I
I
I
I
I
Data inputs for 9-bit bus.
Data outputs for 9-bit bus.
The only write enable to have programmable flags when device is configured. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin
operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data is not written into the
FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD
is held LOW to write or read the programmable flag offsets.
Enables device for read operation.
The rising edge clocks data into the FIFO when WEN1 is LOW, WEN2/LD is HIGH, and
the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
32
3130
29
28
27
26
25
24
23
22
21
RS
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
CY7C4211
Figure 1. Pin Diagram
CC
8
7
6
5
512 × 9
100
-10
0.5
10
35
40
8
3
8
CY7C4221
REN1
RCLK
REN2
GND
PAE
PAF
1K × 9
D
D
1
0
1
2
3
4
5
6
7
8
32
9 10 11 12 13
Description
31 30
Top View
66.7
-15
10
15
10
35
40
TQFP
4
1
CY7C4231
29 28 27
CY7C4421/4201/4211/4221
2K × 9
14 15 16
26
25
24
23
22
21
20
19
18
17
CY7C4231/4241/4251
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
CY7C4241
CC
8
7
6
5
-25
40
15
25
15
35
40
6
1
4K × 9
CY7C4251
Page 3 of 20
ICC1
Unit
MHz
8K × 9
ns
ns
ns
ns
ns
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