CY7C4251-15JCT Cypress Semiconductor Corp, CY7C4251-15JCT Datasheet - Page 11

• Manufacturer Part Number: CY7C4251-15JCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4251-15JCT

• Configuration: Dual
• Density: 64Kb
• Access Time (max): 15ns
• Word Size: 9b
• Organization: 8Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PLCC
• Clock Freq (max): 40MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

Switching Waveforms
Document #: 38-06016 Rev. *D
REN1,REN2
Notes
14. t
15. t
(if applicable)
REN1,REN2
the rising edge of RCLK and the rising edge of WCLK is less than t
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
SKEW1
WEN2
Q
D
WCLK
WEN1
WEN1
WEN2
WCLK
RCLK
0
RCLK
0
–Q
–D
OE
FF
EF
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time between
8
8
t
ENS
t
OLZ
t
SKEW1
t
ENH
[14]
t
t
CLKH
CLKH
t
t
t
WFF
A
REF
t
OE
t
t
CLK
CKL
t
Figure 5. Write Cycle Timing
Figure 6. Read Cycle Timing
SKEW1
NO OPERATION
SKEW1
SKEW1
[15]
t
DS
t
t
CLKL
CLKL
, then FF may not change state until the next WCLK rising edge.
, then EF may not change state until the next RCLK rising edge.
t
ENS
t
VALID DATA
DH
t
ENH
t
REF
t
WFF
CY7C4421/4201/4211/4221
t
OHZ
NO OPERATION
NO OPERATION
CY7C4231/4241/4251
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