AD9937KCPRL Analog Devices Inc, AD9937KCPRL Datasheet - Page 5

• Manufacturer Part Number: AD9937KCPRL
• Manufacturer: Analog Devices Inc

Specifications of AD9937KCPRL

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Not Compliant

TIMING SPECIFICATIONS
Parameter
MASTER CLOCK, VCKM
AFE CLAMP PULSES
AFE SAMPLE LOCATION
DATA OUTPUTS
SERIAL INTERFACE
NOTES
1
2
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Parameter
AVDD
TCVDD
HVDD
RSVDD
DVDD
DRVDD
RS Output
H1(A–D), H2(A, B)Output HVSS
Digital Outputs
Digital Inputs
SCK, SLD, SDA
VRT, VRB
CCDIN
Junction Temperature
Lead Temperature, 10 sec
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9937 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
Parameter is programmable.
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
VCKM Clock Period
VCKM High/Low Pulsewidth
Delay from VCKM Rising Edge to Internal Pixel Position 0
CLPOB Pulsewidth
SHP Sample Edge to SHD Sample Edge
Output Delay from VCLK Rising Edge
Pipeline Delay from SHP/SHD Sampling (See Figure 40)
Maximum SCK Frequency
SLD to SCK Setup Time
SCK to SLD Hold Time
SDA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDA Valid Hold
SCK Falling Edge to SDA Valid Read
2
1
With
Respect
To
AVSS
TCVSS
HVSS
RSVSS
DVSS
DRVSS
RSVSS
DVSS
DVSS
DVSS
AVSS
AVSS
1
(See Figure 13)
Min
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
(C
L
= 20 pF, AVDD = DVDD = DRVDD = 3 V, f
Max
+3.9
+3.9
+3.9
+3.9
+3.9
+3.9
RSVDD + 0.3 V
HVDD + 0.3 V
DVDD + 0.3 V
DVDD + 0.3 V
DVDD + 0.3 V
AVDD + 0.3 V
AVDD + 0.3 V
150
350
Unit
V
V
V
V
V
V
°C
°C
–5–
Symbol
t
t
t
t
f
t
t
t
t
t
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
Model
AD9937KCP
AD9937KCPRL –25°C to +85°C
CONV
VCKMDLY
S1
SCLK
DH
DV
OD
LS
LH
DS
JA
= 24.9°C/W
CLI
= 12 MHz, unless otherwise noted.)
Min
83.33
2
33.34
10
10
10
10
10
10
Temperature
Range
–25°C to +85°C
ORDERING GUIDE
Typ
41.67
9
20
41.67
9
9
Package
Description
Lead Frame
Chip Scale
Package
(LFCSP)
Lead Frame
Chip Scale
Package
(LFCSP)
Max
AD9937
Unit
ns
ns
ns
Pixels
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns
Package
Option
CP-56
CP-56