AD9937KCPRL Analog Devices Inc, AD9937KCPRL Datasheet - Page 22

• Manufacturer Part Number: AD9937KCPRL
• Manufacturer: Analog Devices Inc

Specifications of AD9937KCPRL

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Not Compliant

AD9937
PRECISION TIMING HIGH SPEED TIMING
GENERATION
The AD9937 generates flexible high speed timing signals using
the precision timing core. This core is the foundation for gener-
ating the timing used for both the CCD and the AFE: the
reset gate RS, horizontal drivers H1(A–D) and H2(A, B), and
the CDS sample clocks. A unique architecture makes it routine
for the system designer to optimize image quality by providing
precise control over the horizontal CCD readout and the AFE
correlated double sampling.
Timing Resolution
The precision timing core uses a 13 master clock input
(VCKM) as a reference. This clock should be the same as
the CCD pixel clock frequency. Figure 12 illustrates how
the internal timing core divides the master clock period into
48 steps or edge positions. Using a 12 MHz VCKM fre-
quency, the edge resolution of the precision timing core is
1.7 ns. A 24 MHz VCKM frequency can be applied to the
AD9937 where the AD9937 will internally divide the VCKM
frequency by 2. VCKM frequency division by 2 is controlled
by using the VCKM_DIVIDE control (addr 0x04) register.
POSITION
PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
THERE IS A FIXED DELAY FROM THE VCKM INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
1 PIXEL
PERIOD
VCKM
(INTERNAL)
SIGNAL
t
VCKMDLY
CCD
CDS
RS
H2
H1
1
5
PROGRAMMABLE CLOCK INFORMATION
1. RG RISING EDGE (PROGRAMMABLE AT CONTROL REGISTER RSPOSLOC (ADDR 0x06))
2. RG FALLING EDGE (PROGRAMMABLE AT CONTROL REGISTER RSNEGLOC (ADDR 0x06))
3. SHP SAMPLE LOCATION (PROGRAMMABLE AT CONTROL REGISTER SHPLOC (ADDR 0x05))
4. SHD SAMPLE LOCATION (PROGRAMMABLE AT CONTROL REGISTER SHDLOC (ADDR 0x05))
5. H1 RISING EDGE LOCATION (PROGRAMMABLE AT CONTROL REGISTER H1POSLOC (ADDR 0x06))
6. H1 NEGATIVE EDGE LOCATION (PROGRAMMABLE AT CONTROL REGISTER H1NEGLOC (ADDR 0x06))
7. H2 IS ALWAYS THE INVERSE OF H1.
Figure 12. High Speed Clock Resolution from VCKM Master Clock
P[0]
2
Figure 13. High Speed Clock Programmable Locations
3
6
P[12]
4
–22–
P[24]
High Speed Clock Programmability
Figure 13 shows how the high speed clocks RS, H1–H2, SHP, and
SHD are generated. The RS and H1 pulse have positive and nega-
tive edge programmability by using control registers (addr 0x06).
The H2 clock is always the inverse of H1. Table VIII summarizes
the high speed timing registers and the parameters for the high
speed clocks. Each register is six bits wide with the 2 MSB
used to select the quadrant region as outlined in Table IX.
Figure 14 shows the range and default locations of the high
speed clock signals.
H-Driver and RS Outputs
In addition to the programmable timing positions, the AD9937
features on-chip output drivers for the RS and H1–H2 outputs.
These drivers are powerful enough to directly drive the CCD
inputs. The H-driver current can be adjusted for optimum rise/
fall time into a particular load by using the H1DRV and H2DRV
control registers (addr 0x07). The RS drive current is adjustable
using the RSDRV control register (addr 0x07). The H1DRV,
H2DRV, and RSDRV registers are adjustable in 1.75 mA incre-
ments. All DRV registers have setting of 0 equal to OFF or
three-state, and the maximum setting of 7.
t
VCKMDLY
P[36]
= 6ns TYP).
P[48] = P[0]
REV. 0