AD9937KCPRL Analog Devices Inc, AD9937KCPRL Datasheet - Page 25

• Manufacturer Part Number: AD9937KCPRL
• Manufacturer: Analog Devices Inc

Specifications of AD9937KCPRL

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Not Compliant

MASTER AND SLAVE MODE OPERATION
The AD9937 defaults at power up into slave mode operation.
During slave mode operation, the VD and HD pins are config-
ured as inputs for external VD and HD signals. The AD9937
can be configured into master mode operation to output the
VD and HD signals by programming MASTER = 1 (control
addr 0x05).
HORIZONTAL AND VERTICAL TIMING
The internal VD and HD synchronization timing is configured
by using the registers in Table X. As shown in Figure 17, the
HD and VD clock positions are referenced to the 12-bit
H-counter and 11-bit V-counter, respectively. This allows for
a maximum of 4096 horizontal pixels by 2048 vertical
line resolution.
The AD9937 provides programmability for two HD pulses per
line with the ability to independently set the last line length by
using the HDLASTLEN register (Mode_Reg(4)). Additionally,
the HDLENx (where x = 0, 1, 2, 3, 4 representing CCD regions)
registers can be used to set different line lengths for each CCD
region. As shown in Figure 31, up to five unique CCD regions
may be specified.
Register Name
VDLEN
VDTOG1
VDTOG2
HDTOG1
HDTOG2
HDTOG3
HDTOG4
HDLASTLEN
HDLEN0
HDLEN1
HDLEN2
HDLEN3
HDLEN4
VDHD_INVERT
REV. 0
Length
(Bits)
11
4
4
12
12
12
12
12
12
12
12
12
12
1
Register Type
Mode_Reg(4)
Mode_Reg(4)
Mode_Reg(4)
Mode_Reg(2)
Mode_Reg(2)
Mode_Reg(3)
Mode_Reg(3)
Mode_Reg(4)
Mode_Reg(15)
Mode_Reg(16)
Mode_Reg(17)
Mode_Reg(18)
Mode_Reg(19)
Control 0x04
Table X. HD and VD Registers
Range
0–2047 Line Number
0–15 Pixel Location
0–15 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
HIGH/LOW
–25–
Individual HMASK Sequence
The HMASK programmable timing shown in Figure 18 pro-
vides two HMASK toggle positions and an H1MASK polarity
setting. These registers can be used to disable the horizontal
H1 and H2 outputs during the vertical transfer period. As shown
in Figure 18, the H2(A, B) outputs are always the opposite
polarity of the H1(A–D) outputs. The H1MASKSTART and
H1MASKSTOP registers reference the 11-bit VD counter.
Individual PBLK Sequences
Up to two individual PBLK pulses can be programmed per line
using the registers in Table XI. During the time PBLK is active,
the DOUT[9:0] data is fixed at the level set in the PBLK_LEVEL
(control addr 0x03) register. Figures 19, 20, and 21 provide
examples of PBLK registers described in Table XI.
Description
11-Bit VD Counter Length
VD Toggle Position 1. See Figure 17.
VD Toggle Position 2. See Figure 17.
HD Toggle Position 1. See Figure 17.
HD Toggle Position 2. See Figure 17.
HD Toggle Position 3. See Figure 17.
HD Toggle Position 4. See Figure 17.
HD Last Line Length. See Figure 17.
12-Bit HD Counter Length Value for CCD Region 0
12-Bit HD Counter Length Value for CCD Region 1
12-Bit HD Counter Length Value for CCD Region 2
12-Bit HD Counter Length Value for CCD Region 3
12-Bit HD Counter Length Value for CCD Region 4
VD and HD Inversion Control
AD9937