FAGD16556ECLBA Intel, FAGD16556ECLBA Datasheet - Page 7

• Manufacturer Part Number: FAGD16556ECLBA
• Manufacturer: Intel

Specifications of FAGD16556ECLBA

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

This has been realised by counting the
false bit transitions. If this counter runs
out within a time period the BEF flag is
set. The length of the counter may be set
by external select signals (SBER0 and
SBER1). The time period that the false
errors are counted within is 64 kbit/s cor-
responding to 26 ms at STM 16 / OC-48
data rate. The length of the counter may
be set to detect approximate Bit Error
Rates of 0.5E-3, 1E-3, 2E-3 or 4E-3.
The input to the BEF circuit is derived
from Bang-Bang detector sample data.
As discussed above, the Bang-Bang de-
tector samples the incoming data twice
each bit period, once at the transition and
once in the middle of the eye. If the value
of the samples in the middle of the eye
for two consecutive bits is equal but the
value of the transition sample is different
then a bit error has occurred.
As the BEF system detects false bit tran-
sitions between two consecutive bits,
only bit errors due to high frequency
noise are detected. Therefore there will
not be a 1:1 correlation between the ac-
tual BER of the signal and the number of
errors detected by the BEF system. How-
ever the actual bit error rate is correlated
to the number of errors detected in the
BEF system. This means that by choos-
ing the appropriate counter length, it will
be possible for the BEF system to set the
BEF flag at a user selectable bit error
rate.
Once the LOS_DET signal has been as-
serted, it will be de-asserted only when
the BER is less than ¼ of the set rate for
a period which is proportional to the se-
lected data rate. (at least 125 ms at
STM16 / OC-48).
Data Input
The input amplifier (DI / DIN) is designed
as a Limiting Amplifier (LIA) with a sensi-
tivity better than 10 mV (differential).
The inputs may be either AC or DC cou-
pled. If the inputs are AC coupled the
amplifier features an internal offset can-
celling DC feedback. Notice that the off-
set cancellation will only work when the
input is differential and AC-coupled as
shown on
Bit Order
The serial data stream is output with the
first bit received on DO0, the second on
DO1 and the last bit in a 16 bit frame on
DO15.
Data Sheet Rev.: 23
Figure 12.
Figure 12.AC coupled input (using internal offset compensation).
Figure 13.DC coupled input (ignoring internal offset compensation). V
GD16556/GD16557*
the termination requirements of the previous stage, and the resulting ampli-
tude on the input.
From LINE
From LINE
From LINE
From LINE
VEE
VEE
VTT
VTT
DI
DI
DIREF
DIREFN
DIN
DIREF
DIREFN
DIN
50R
50R
50R
50R
+
-
+
-
26dB
26dB
8k
8k
8k
8k
TT
depends on
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