FAGD16556ECLBA Intel, FAGD16556ECLBA Datasheet - Page 15

• Manufacturer Part Number: FAGD16556ECLBA
• Manufacturer: Intel

Specifications of FAGD16556ECLBA

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

Note:
End of GD16556 Pin List
Data Sheet Rev.: 23
Mnemonic:
CKREFB, CKREFBN
CKRSEL
CDRSEL
TCK
SELTCK
LD_SEL
SBER0, SBER1
LOCK
BC_DET
LOS_DET
LOCKDET
FCK, FCKN
VCTL
OUCHP
VDD
VDDV
VDDL
VDDO
VDDP
VEE
VEEL
VEEP
VEEV
Heat sink
*
indicates that the pin is available as LVPECL I/O. Please refer to LVPECL characteristics and
2, 9, 18, 25, 26,
27, 78, 84, 85,
32, 51, 82, 88,
3, 19, 24, 31,
33, 50, 68
Pin No.:
81, 80
21, 22
77, 76
89, 93
10, 11
12, 15
100
83
73
95
94
23
79
28
29
30
99
92
98
96
97
1
PCMOS output
PCMOS output
PCMOS output
PCMOS output
PCMOS output
ANALOG input
LVPECL input
LVDS output
LVTTL input
LVTTL input
LVTTL input
LVTTL input
LVTTL input
LVDS input
Pin Type:
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
*.
*.
GD16556/GD16557*
Differential. CDR reference clock. In transponder systems
CKREFA or CKREFB should be connected to the output signal
RECCK from the GD16557 device. The input impedance is 100 W
differential. (100 W on-chip termination resistor).
Reference input clock select pin.
The pin is supplied with a 16 kW pull-up resistor.
“1”: Selects CKREFA, CKREFAN
“0”: Selects CKREFB, CKREFBN.
Lock-select for CDR setup.
The pin is supplied with a 16 kW pull-up resistor.
“0" selects Manual Phase Freq. detector
“1" selects Auto-lock, 500 ppm (default)
Leave open for normal operation. Only used at DC test.
Test-clock select. Connect to VDD for normal operation. Only
used for test purposes.
Select of count.
“0” Double the time that LOCKDET remains high.
“1” Normal mode (default).
BER select inputs.
SBER0 SBER1 BER-level
0
0
1
1
A high level indicates that the PLL is locked to the incoming serial
data. A low level indicates out of lock. When the GD16556 cannot
acquire lock to the serial data this signal switches between ”0"
and “1"
VCO frequency deviates more than 500 ppm from reference fre-
quency, or BC_DET is asserted.
Differential. Forward reference clock for transmitter in transponder
system. In transponder systems connect this pin to the input CKI
on the GD16557 device. The differential output impedance is
100 W. The LVDS output must be terminated with an 100 W im-
pedance DC-path between the differential output.
VCO control voltage pin.
Charge pump output to be connected to loop-filter.
+3.3 V Positive power supply for core logic and I/O
+3.3 V Positive supply for VCO. To be connected to the loop-filter.
+3.3 V Positive supply for Limiting Amplifier.
+3.3 V Positive supply for Outputs.
+3.3 V Positive supply for Charge Pump.
0 V Ground. The heat sink must be connected to VEE by a
soldered connections.
0 V for Limiting Amplifier.
0 V for Charge Pump.
0 V Ground for VCO.
Connected to VEE by soldering.
Description:
Bit consecutive detect output (logic High).
Loss Of Signal detect (alarm = logic High) output.
Valid data loss detect (alarm) output. Asserted when the divided
0
1
0
1
0.5 × 10
1 × 10
2 × 10
4 × 10
-3
-3
-3
-3
Figures 6
and
Page 15 of 28
7
.