FAGD16556ECLBA Intel, FAGD16556ECLBA Datasheet - Page 18

• Manufacturer Part Number: FAGD16556ECLBA
• Manufacturer: Intel

Specifications of FAGD16556ECLBA

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

Note:
End of GD16557 Pin List.
Data Sheet Rev.: 23
Mnemonic:
VCTL
VCXOCHAP
VCOCHAP
DO, DON
CKO, CKON
CNTCK, CNTCKN
RECCK, RECCKN
MSEL1, MSEL2
CKTST
TSTMODE
LOCK1, LOCK2
LOCK1A, LOCK2A
VCMLT1
VCMLT2
VCMLT3
VDD
VDDA
VEE
VEEA
Heat sink
*
indicates that the pin is available as LVPECL I/O. Please refer to LVPECL characteristics and
33, 51, 69, 73, 76,
50, 68, 72, 79, 97
8, 10, 14, 20, 30,
3, 12, 16, 24, 26,
Pin no.:
13, 15
31, 32
71, 70
81, 80
91, 93
90, 92
88, 94
11, 9
100
99
89
98
96
95
18
22
28
1
PCMOS output.
PCMOS output.
ANALOG input.
PCMOS output
LVPECL input
LVTTL output
LVDS output
LVDS output
LVTTL input
LVTTL input
Termination
CML output
CML output
Pin type:
PWR
PWR
PWR
PWR
*.
*.
GD16556/GD16557*
Description:
Voltage Control pin for VCO. Connect the VCO loop-filter to this
pin.
Connect the VCXO loop-filter to this pin. This output will source
current when the VCXO increases the frequency and sink current
when the VCXO decreases the frequency. Otherwise the output
tristates (high impedance).
Charge Pump output for VCO. Connect the VCO loop-filter to this
pin. The loop-filter should be terminated to VDDA. This output will
sink current when the VCO increases the frequency and source
current when the VCO decreases the frequency. Otherwise the
output tristates (high impedance).
Differential. High speed serial data output. Terminated with 50 W
to VDD on-chip.
Differential. High speed clock output. Terminated with 50 W to
VDD on-chip.
Differential. Counter clock for input data. Output impedance is
100 W differential. The LVDS output must be terminated with an
100 W impedance DC-path between the differential output.
Differential. Reference clock output for CDR device GD16556. To
be used in transponder systems only. In transponder systems
connect this output to the GD16556 input CKREF. Output imped-
ance is 100 W differential. The LVDS output must be terminated
with an 100 W impedance DC-path between the differential out-
put.
Select for 15/14, 16/15 and 32/31 overhead bit rates. These pins
select the divide ratio tuning the on-chip VCO frequency. The pins
are supplied with a 16 kW pull-up resistor.
Divide by
56
60
62
64 (default)
Refer to Table 1 on
applic.
Test clock input. To be used for test purposes only.
Test mode select pin. To be used for test purposes only.
The pin is supplied with a 16 kW pull-up resistor. A logic “0" se-
lects test mode. When not connected the signal defaults to a logic
”1".
PLL lock-detect signals. LOCK1 monitors the VCXO based PLL
and LOCK2 monitors the VCO based PLL. A logic “1" indicates no
lock and a logic ”0" indicates lock. Connect these pins to a 10 nF
capacitance.
Buffered lock detect signal.
CML input termination pin. Connect these pins to the positive
supply. Refer to
+3.3 V Power supply for core and I/O
+3.3 V Power supply for VCO. To be connected to the loop-filter.
0 V Ground. The heat sink must be connected to VEE by a
soldered connection.
0 V Ground for VCO.
Connected to VEE by soldering.
Figure
MSEL1 MSEL2
0
0
1
1
page 11
9.
0
1
0
1
for configuration in transponder
Figures 6
and 7.
Page 18 of 28