82P2821BH IDT, Integrated Device Technology Inc, 82P2821BH Datasheet - Page 66

• Manufacturer Part Number: 82P2821BH
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2821BH

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.6.3
should be a clock with +/-32 ppm (in T1/J1 mode) or +/-50 ppm (in E1
mode) accuracy. The clock frequency of MCLK is set by pins
MCKSEL[3:0] and can be N x 1.544 MHz or N x 2.048 MHz with 1 ≤ N ≤
8 (N is an integer number). Refer to MCKSEL[3:0] pin description for
details.
device will enter power down. In this case, both the receive and transmit
circuits are turned off. The pins on the line interface will be in High-Z
state. The pins on receive system interface will be in High-Z state or in
low level, as selected by the RHZ bit (b6, RCF0,...). The input on the
Functional Description
IDT82P2821
MCLK provides a stable reference timing for the IDT82P2821. MCLK
If there is a loss of MCLK (duty cycle is less than 30% for 10 µs), the
MCLK, MASTER CLOCK INPUT
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
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transmit system interface is ignored and the output on the transmit
system interface will be in High-Z state. Refer to Section 3.2.7 Receiver
Power Down and Section 3.3.7 Transmitter Power Down for details.
matically.
3.6.4
MHz in T1/J1 mode or 2.048 MHz in E1 mode. XCLK is used as select-
able reference clock for
If MCLK recovers after loss of MCLK the device will be reset auto-
XCLK is derived from MCLK. For the respective channel, it is 1.544
• pattern /AIS generation
• RCLKn in LLOS
• Loss of TCLKn to determine Transmit Output High-Z.
XCLK, INTERNAL REFERENCE CLOCK INPUT
February 6, 2009