82P2821BH IDT, Integrated Device Technology Inc, 82P2821BH Datasheet - Page 62

• Manufacturer Part Number: 82P2821BH
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2821BH

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.6.2
determined by the REFA_EN bit (b6, REFA) and the REFB_EN bit (b6,
REFB) respectively.
different operations. Refer to below for detailed description. Refer to
Figure-40 and Figure-41 for an overview of REFA and REFB output
options in normal operation.
3.6.2.1 REFA/REFB in Clock Recovery Mode
the recovered clock of one of the 22 channels as selected by the
REFA[4:0] bits (b4~0,REFA) and REFB[4:0] bits (b4~0,REFB). Deter-
mined by the FS_BYPAS bit (b4, REFCF) a Frequency Synthesizer can
be enabled for REFA (refer to Section 3.6.2.2 Frequency Synthesizer for
REFA Clock Output). If the Frequency Synthesizer is disabled, REFA
will output the recovered 1.544 MHz (T1) or 2.048 MHz (E1) clock
depending on the line mode of the selected channel. REFB output the
recovered 1.544 MHz (T1) or 2.048 MHz (E1) clock depending on the
line mode of the selected channel.
after it passed the receive Jitter Attenuator (RJA) selected by the
JA_BYPAS bit (b6, REFCF).
3.6.2.2 Frequency Synthesizer for REFA Clock Output
(default) as selected by FS_BYPASS bit (b4, REFCF). The output
frequency is selected by the FREQ[2:0] bits (b2~0, REFCF). Frequen-
cies supported are 8 KHz, 64 KHz, 2.048 MHz, 4.096 MHz, 8.192 MHz,
19.44 MHz or 32.768 MHz.
3.6.2.3 Free Run Mode for REFA Clock Output
MCLK. To enable this mode the Frequency Synthesizer has to be
enabled by setting the FS_BYPAS bit (b4, REFCF) to ‘0’, and the FREE
bit (b3, REFCF) has to be set to ‘1’. REFA will provide a frequency
selected by the FREQ[2:0]
clock locked to MCLK.
3.6.2.4 REFA/REFB Driven by External CLKA/CLKB Input
clock input of CLKA and CLKB respectively. CLKA and CLKB are
selected as an input source by setting REFA[4:0] bits (b4~0, REFA) and
REFB[4:0] bits (b4~0, REFB) to any value from ‘11101’ to ‘11111’.
Functional Description
IDT82P2821
The outputs on REFA and REFB can be enabled or disabled, as
When the output is disabled, REFA/REFB is in High-Z state.
When the output is enabled, the output of REFA and REFB varies in
In this mode (default), the clock of REFA and REFB is derived from
The recovered line clock can be output to REFA and REFB before or
For REFA a Frequency Synthesizer can be enabled or bypassed
REFA can also be selected to provide a free running clock locked to
In this mode, the clock of REFA and REFB is driven from an external
1. ‘000’ and ‘011’ are reserved for FREQ[2:0] in this mode.
CLOCK OUTPUTS ON REFA/REFB
1
bits (b2~0, REFCF) which is a free running
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
62
MHz) Clock Input. The CKA_T1E1 bit (b5, REFA) and CKB_T1E1 bit
(b5, REFB) should be set to match the input clock frequency.
Synthesizer can be enabled for REFA (refer to Section 3.6.2.2
Frequency Synthesizer for REFA Clock Output). If the Frequency
Synthesizer is disabled, REFA will output the 1.544 MHz (T1) or 2.048
MHz (E1) clock depending the CLKA input clock. REFB will output 1.544
MHz (T1) or 2.048 MHz (E1) depending on the CLKB input clock.
3.6.2.5 REFA and REFB in Loss of Signal (LOS) or Loss of Clock
Condition
clock source for REFA and REFB (refer to Section 3.6.2.1 REFA/REFB
in Clock Recovery Mode) and Line LOS (LLOS) is detected in the corre-
sponding channel, the state of output on REFA and REFB can be
selected by the REFH bit (b5, REFCF). If REFH is set to ‘1’, REFA and
REFB will output a high level in case of LLOS. If REFH is set to ‘0’ and
LLOS is detected, REFA and REFB clock outputs will be locked to
MCLK while the selected clock frequency will remain unchanged.
Section 3.5.3.1 Line LOS (LLOS).
LLOS. REFB output option is only determined by the REFH bit (b5,
REFCF) to be locked to MCLK or set to high level output.
Section 3.6.2.4 REFA/REFB Driven by External CLKA/CLKB Input) and
there is no clock input on CLKA for more than 8 T1 clock cycles if T1
mode is selected (i.e. CKA_T1E1 bit (b5, REFA) is ‘0’) or more than 8 E1
clock cycles if E1 mode is selected (i.e. CKA_T1E1 bit (b5, REFA) is ‘1’),
the state of the REFA output is determined by the FS_BYPAS bit (b4,
REFCF) and the FREE bit (b3, REFCF). In case the Frequency Synthe-
sizer is disabled (i.e. FS_BYPAS bit (b4, REFCF) is ‘0’). REFA will
output a high level. If the Frequency Synthesizer is enabled and the
FREE bit (b3, REFCF) is set to ‘0’, REFA will output a high level. If the
Frequency Synthesizer is enabled and the FREE bit (b3, REFCF) is set
to ‘1’, REFA will be locked to MCLK.
loss of CLKA.
Section 3.6.2.4 REFA/REFB Driven by External CLKA/CLKB Input) and
there is no clock input on CLKB for more than 8 T1 clock cycles if T1
mode is selected (i.e. CKB_T1E1 bit (b5, REFB) is ‘0’) or more than 8
E1 clock cycles if E1 mode is selected (i.e. CKB_T1E1 bit (b5, REFB) is
‘1’), the output on REFB is determined by the REFH bit (b5, REFCF). If
REFH is set to ‘1’, REFB will output a high level. If REFH is set to ‘0’, the
REFB clock output will be locked to MCLK.
CLKA and CLKB are an external T1/J1 (1.544 MHZ) or E1 (2.048
Determined by the FS_BYPASS bit (b4, REFCF), a Frequency
If the recovered clock of one of the 22 channels is selected as the
LLOS condition is set when LLOS_S bit (b0, STAT0) is ‘1’. Refer to
Refer to Figure-42 for a detailed overview of REFA output in case of
If CLKA is selected as the clock source for REFA (refer to
Refer to Figure-43 for a detailed overview of REFA output in case of
If CLKB is selected as the clock source for REFB (refer to section
February 6, 2009