82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 4

• Manufacturer Part Number: 82V2042EPF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2042EPF8

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

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Table of Contents
IDT82V2042E
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
PROGRAMMING INFORMATION .............................................................................................. 42
4.1
4.2
4.3
HARDWARE CONTROL PIN SUMMARY .................................................................................. 59
IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 61
6.1
6.2
3.8.3 REMOTE LOOPBACK............................................................................................ 33
3.8.4 INBAND LOOPBACK.............................................................................................. 34
ERROR DETECTION/COUNTING AND INSERTION ...................................................... 36
3.9.1 DEFINITION OF LINE CODING ERROR ............................................................... 36
3.9.2 ERROR DETECTION AND COUNTING ................................................................ 36
3.9.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 37
LINE DRIVER FAILURE MONITORING ........................................................................... 37
MCLK AND TCLK ............................................................................................................. 38
3.11.1 MASTER CLOCK (MCLK) ...................................................................................... 38
3.11.2 TRANSMIT CLOCK (TCLK).................................................................................... 38
MICROCONTROLLER INTERFACES ............................................................................. 39
3.12.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 39
3.12.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 39
INTERRUPT HANDLING .................................................................................................. 40
5V TOLERANT I/O PINS .................................................................................................. 41
RESET OPERATION ........................................................................................................ 41
POWER SUPPLY ............................................................................................................. 41
REGISTER LIST AND MAP ............................................................................................. 42
Reserved Registers .......................................................................................................... 42
REGISTER DESCRIPTION .............................................................................................. 44
4.3.1 GLOBAL REGISTERS............................................................................................ 44
4.3.2 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 45
4.3.3 JITTER ATTENUATION CONTROL REGISTER ................................................... 45
4.3.4 TRANSMIT PATH CONTROL REGISTERS........................................................... 46
4.3.5 RECEIVE PATH CONTROL REGISTERS ............................................................. 48
4.3.6 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 49
4.3.7 INTERRUPT CONTROL REGISTERS ................................................................... 52
4.3.8 LINE STATUS REGISTERS ................................................................................... 55
4.3.9 INTERRUPT STATUS REGISTERS ...................................................................... 57
4.3.10 COUNTER REGISTERS ........................................................................................ 58
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 62
JTAG DATA REGISTER ................................................................................................... 62
6.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 62
6.2.2 BYPASS REGISTER (BR)...................................................................................... 62
6.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 62
3.8.4.1 Transmit Activate/Deactivate Loopback Code......................................... 34
3.8.4.2 Receive Activate/Deactivate Loopback Code.......................................... 34
3.8.4.3 Automatic Remote Loopback .................................................................. 35
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
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December 12, 2005