82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 32

• Manufacturer Part Number: 82V2042EPF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2042EPF8

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.7
Activate/Deactivate Loopback Code) will be generated and detected by
IDT82V2042E. TCLKn is used as the reference clock by default. MCLK can
also be used as the reference clock by setting the PATT_CLK bit (MAINT0,
0CH...) to ‘1’.
(MAINT0, 0CH...) are set to ‘00’, the transmit path will operate in normal
mode.
in normal mode by setting PATTn[1:0] pins to ‘00’ on a per channel basis.
Refer to
3.7.1
stream when the PATT[1:0] bits (MAINT0, 0CH...) are set to ‘01’. The trans-
mit data stream is output from TTIPn/TRINGn. In this case, either TCLKn
or MCLK can be used as the transmit clock, as selected by the PATT_CLK
bit (MAINT0, 0CH...).
stream in transmit direction by setting PATTn[1:0] pins to ‘01’ on a per chan-
nel basis. Refer to
3.7.2
inserted into the transmit data stream when the PATT[1:0] bits (MAINT0,
0CH...) are set to ‘00’.
3.7.3
in the receive direction by IDT82V2042E. The QRSS is 2
applications and the PRBS is 2
restrictions according to the AT&T TR62411 and ITU-T O.151.
QRSS pattern will be inserted into the transmit data stream with the MSB
first. The PRBS/QRSS pattern will be transmitted directly or invertedly.
mit direction and inserted into the transmit data stream by setting
PATTn[1:0] pins to ‘10’ on a per channel basis. Refer to
TROL PIN SUMMARY
PRBS/QRSS has reached synchronization status, the PRBS_S bit
(STAT0, 16H...) will be set to ‘1’, even in the presence of a logic error rate
less than or equal to 10
are shown in Table-16.
FUNCTIONAL DESCRIPTION
IDT82V2042E
The internal patterns (All Ones, All Zeros, PRBS/QRSS pattern and
If the PATT_CLK bit (MAINT0, 0CH...) is set to ‘0’ and the PATT[1:0] bits
When the chip is configured by hardware, the transmit path will operate
In transmit direction, the All Ones data can be inserted into the data
In hardware control mode, the All Ones data can be inserted into the data
If the PATT_CLK bit (MAINT0, 0CH...) is set to ‘1’, the All Zeros will be
A PRBS/QRSS will be generated in the transmit direction and detected
When the PATT[1:0] bits (MAINT0, 0CH...) are set to ‘10’, the PRBS/
In hardware control mode, the PRBS data will be generated in the trans-
The PRBS/QRSS in the received data stream will be monitored. If the
TRANSMIT AND DETECT INTERNAL PATTERNS
TRANSMIT ALL ONES
TRANSMIT ALL ZEROS
PRBS/QRSS GENERATION AND DETECTION
5 HARDWARE CONTROL PIN SUMMARY
5 HARDWARE CONTROL PIN SUMMARY
for details.
-1
. The criteria for setting/clearing the PRBS_S bit
15
-1 for E1 applications, with maximum zero
for details.
5 HARDWARE CON-
for details.
20
-1 for T1/J1
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
32
Table-16 Criteria for Setting/Clearing the PRBS_S Bit
0CH...).
18H...). The PRBS_IES bit (INTES, 15H...) can be used to determine
whether the ‘0’ to ‘1’ change of PRBS_S bit will be captured by the PRBS_IS
bit or any changes of PRBS_S bit will be captured by the PRBS_IS bit. When
the PRBS_IS bit is ‘1’, an interrupt will be generated if the PRBS_IM bit
(INTM0, 13H...) is set to ‘1’.
counter if the ERR_SEL [1:0] bits (MAINT6, 12H...) are set to ‘00’. Refer to
3.9 ERROR DETECTION/COUNTING AND INSERTION
of the error counter.
3.8
ferent loopback configurations: Analog Loopback, Digital Loopback,
Remote Loopback and Inband Loopback.
3.8.1
nel is configured in Analog Loopback mode. In this mode, the transmit sig-
nals are looped back to the Receiver Internal Termination in the receive
path then output from RCLKn, RDn, RDPn/RDNn. The all-ones pattern can
be generated during analog loopback. At the same time, the transmit sig-
nals are still output to TTIPn/TRINGn in transmit direction.
the process.
LPn[1:0] pins to ‘01’ on a per channel basis.
3.8.2
nel is configured in Digital Loopback mode. In this mode, the transmit sig-
nals are looped back to the jitter attenuator (if enabled) and decoder in
receive path, then output from RCLKn, RDn, RDPn/RDNn. At the same
time, the transmit signals are still output to TTIPn/TRINGn in transmit direc-
tion.
sending of the internal patterns (All Ones, All Zeros, PRBS, etc.) which will
overwrite the transmit signals. In this case, either TCLKn or MCLK can be
used as the reference clock for internal patterns transmission.
LPn[1:0] pins to ‘10’ on a per channel basis.
PRBS/QRSS
Detection
PRBS/QRSS
Missing
PRBS data can be inverted through setting the PRBS_INV bit (MAINT0,
Any change of PRBS_S bit will be captured by PRBS_IS bit (INTS0,
The received PRBS/QRSS logic errors can be counted in a 16-bit
To facilitate testing and diagnosis, the IDT82V2042E provides four dif-
When the ALP bit (MAINT1, 0DH...) is set to ‘1’, the corresponding chan-
In hardware control mode, Analog Loopback can be selected by setting
When the DLP bit (MAINT1, 0DH...) is set to ‘1’, the corresponding chan-
Both Analog Loopback mode and Digital Loopback mode allow the
In hardware control mode, Digital Loopback can be selected by setting
Figure-15
LOOPBACK
ANALOG LOOPBACK
DIGITAL LOOPBACK
shows the process.
6 or less than 6 bit errors detected in a 64 bits hopping win-
dow.
More than 6 bit errors detected in a 64 bits hopping window.
December 12, 2005
Figure-14
for the operation
shows