82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet
82V2042EPF8
Specifications of 82V2042EPF8
Related parts for 82V2042EPF8
82V2042EPF8 Summary of contents
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DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT FEATURES: • Dual channel T1/E1/J1 short haul line interfaces • Supports HPS (Hitless Protection Switching) for 1+1 protection without external relays • Programmable T1/E1/J1 switchability allowing one bill of ma- terial for ...
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IDT82V2042E FUNCTIONAL BLOCK DIAGRAM LOSn LOS/AIS Detector RCLKn B8ZS/ RDn/RDPn HDB3/AMI Attenuator CVn/RDNn Decoder PRBS Detector Remote IBLC Detector Loopback TCLKn B8ZS/ TDn/TDPn HDB3/AMI TDNn Decoder PRBS Generator IBLC Generator TAOS Clock Software Control Interface Generator FUNCTIONAL BLOCK DIAGRAM DUAL ...
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IDT82V2042E PIN CONFIGURATIONS ....................................................................................... 9 2 PIN DESCRIPTION ..................................................................................................................... 10 3 FUNCTIONAL DESCRIPTION .................................................................................................... 18 3.1 CONTROL MODE SELECTION ....................................................................................... 18 3.2 T1/E1/J1 MODE SELECTION .......................................................................................... 18 3.3 TRANSMIT PATH ............................................................................................................. 18 3.3.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 18 3.3.2 ...
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IDT82V2042E 3.8.3 REMOTE LOOPBACK............................................................................................ 33 3.8.4 INBAND LOOPBACK.............................................................................................. 34 3.8.4.1 Transmit Activate/Deactivate Loopback Code......................................... 34 3.8.4.2 Receive Activate/Deactivate Loopback Code.......................................... 34 3.8.4.3 Automatic Remote Loopback .................................................................. 35 3.9 ERROR DETECTION/COUNTING AND INSERTION ...................................................... 36 3.9.1 DEFINITION OF LINE CODING ERROR ...
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IDT82V2042E 6.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 62 7 TEST SPECIFICATIONS ............................................................................................................ 65 8 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 78 8.1 SERIAL INTERFACE TIMING .......................................................................................... 78 8.2 PARALLEL INTERFACE TIMING ..................................................................................... 79 Table of Contents DUAL CHANNEL T1/E1/J1 SHORT HAUL ...
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Table-1 Pin Description .............................................................................................................. 10 Table-2 Transmit Waveform Value For E1 75 Ohm ................................................................... 21 Table-3 Transmit Waveform Value For E1 120 Ohm ................................................................. 21 Table-4 Transmit Waveform Value For T1 0~133 ft................................................................... 21 Table-5 Transmit Waveform Value For T1 ...
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IDT82V2042E Table-42 INTM0: Interrupt Mask Register 0 ................................................................................. 52 Table-43 INTM1: Interrupt Masked Register 1 ............................................................................. 53 Table-44 INTES: Interrupt Trigger Edge Select Register ............................................................. 54 Table-45 STAT0: Line Status Register 0 (real time status monitor)............................................. 55 Table-46 STAT1: Line ...
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Figure-1 Block Diagram ................................................................................................................. 2 Figure-2 IDT82V2042E TQFP80 Package Pin Assignment .......................................................... 9 Figure-3 E1 Waveform Template Diagram .................................................................................. 19 Figure-4 E1 Pulse Template Test Circuit ..................................................................................... 19 Figure-5 DSX-1 Waveform Template .......................................................................................... 19 Figure-6 T1 Pulse Template Test Circuit ...
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IDT82V2042E 1 IDT82V2042E PIN CONFIGURATIONS VDDT1 61 TRING1 62 TTIP1 63 GNDT1 64 GNDR1 65 RRING1 66 RTIP1 67 VDDR1 68 VDDA REF 71 GNDA 72 VDDR2 73 RTIP2 74 RRING2 75 76 GNDR2 GNDT2 77 78 ...
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IDT82V2042E 2 PIN DESCRIPTION Table-1 Pin Description Name Type Pin No. TTIP1 Analog 63 TTIPn TTIP2 Output 78 These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A logic high ...
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IDT82V2042E Table-1 Pin Description (Continued) Name Type Pin No. RD1/RDP1 O 34 RDn: Receive Data output for Channel 1~2 RD2/RDP2 26 In single rail mode, this pin outputs NRZ data. The data is decoded according to AMI, HDB3 or B8ZS ...
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IDT82V2042E Table-1 Pin Description (Continued) Name Type Pin No. MODE1 I 9 MODE[1:0]: operation mode of control interface select MODE0 10 The level on this pin determines which control mode is used to control the device as follows: • • ...
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IDT82V2042E Table-1 Pin Description (Continued) Name Type Pin No. SCLK I 46 SCLK: Shift Clock In serial microcontroller interface mode, this signal is the shift clock for the serial interface. Configuration data on SDI pin is sampled on the rising ...
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IDT82V2042E Table-1 Pin Description (Continued) Name Type Pin No. SDO O 43 SDO: Serial Data Output In serial microcontroller interface mode, this signal is the output data of the serial interface. Configuration or Status data at SDO pin is clocked ...
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IDT82V2042E Table-1 Pin Description (Continued) Name Type Pin No. D0 I/O 47 D0: Data Bus bit0 In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should ...
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IDT82V2042E Table-1 Pin Description (Continued) Name Type Pin No. JA1 I 16 JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select for channel 1 and channel 2 (only used in hardware control mode) • • • • In ...
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IDT82V2042E Table-1 Pin Description (Continued) Name Type Pin No. VDDT1 - 61 3.3 V power supply for transmitter driver VDDT2 80 GNDT1 - 64 Analog ground for transmitter driver GNDT2 77 VDDR1 - 68 Power supply for receive analog circuit ...
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IDT82V2042E 3 FUNCTIONAL DESCRIPTION 3.1 CONTROL MODE SELECTION The IDT82V2042E can be configured by software or by hardware. The software control mode supports Serial Control Interface, Motorola non-Mul- tiplexed Control Interface and Intel non-Multiplexed Control Interface. The Control mode is ...
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IDT82V2042E ...
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IDT82V2042E 3.3.3.2 User-Programmable Arbitrary Waveform When the PULS[3:0] bits are set to ‘11xx’, user-programmable arbitrary waveform generator mode can be used in the corresponding channel. This allows the transmitter performance to be tuned for a wide variety of line con- ...
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IDT82V2042E The following tables give all the sample data based on the preset pulse templates in detail for reference. For preset pulse templates, scaling up/ down against the pulse amplitude is not supported. Transmit Waveform Value for E1 75 Ω ...
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IDT82V2042E Table-5 Transmit Waveform Value For T1 133~266 ft Sample 0011011 1000011 2 0101110 1000010 3 0101100 1000001 4 0101010 0000000 5 0101001 0000000 6 0101000 0000000 7 0100111 0000000 8 0100110 0000000 9 0100101 ...
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IDT82V2042E Table-9 Transmit Waveform Value For J1 0~655 ft Sample 0010111 1000010 2 0100111 1000001 3 0100111 0000000 4 0100110 0000000 5 0100101 0000000 6 0100101 0000000 7 0100101 0000000 8 0100100 0000000 9 0100011 ...
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IDT82V2042E 3.4 RECEIVE PATH The receive path consists of Receive Internal Termination, Monitor Gain, Amplitude/Wave Shape Detector, Digital Tuning Controller, Adaptive Equalizer, Data Slicer, CDR (Clock & Data Recovery), Optional Jitter Atten- uator, Decoder and LOS/AIS Detector. Refer to Figure-7. ...
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IDT82V2042E In hardware control mode, TERMn, PULSn[3:0] pins can be used to select impedance matching for both receiver and transmitter on a per chan- nel basis. If TERMn pin is low, internal impedance network will be used. If TERMn pin ...
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IDT82V2042E 3.4.3 ADAPTIVE EQUALIZER The Adaptive Equalizer can be enabled to increase the receive sensi- tivity and to allow programming of the LOS level up to -24 dB. See section 3.6 LOS AND AIS DETECTION. It can be enabled or ...
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IDT82V2042E 3.4.10 G.772 NON-INTRUSIVE MONITORING In applications using only one channel, channel 1 can be configured to monitor the data received or transmitted in channel 2. The MONT[1:0] bits (GCF, 20H) determine which direction (transmit/receive) will be monitored. The monitoring ...
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IDT82V2042E 3.5 JITTER ATTENUATOR There is one Jitter Attenuator in each channel of the LIU. The Jitter Atten- uator can be deployed in the transmit path or the receive path, and can also be disabled. This is selected by the ...
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IDT82V2042E 3.6 LOS AND AIS DETECTION 3.6.1 LOS DETECTION The Loss of Signal Detector monitors the amplitude of the incoming sig- nal level and pulse density of the received signal on RTIPn and RRINGn. • LOS declare (LOS=1) A LOS ...
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IDT82V2042E Table-13 LOS Declare and Clear Criteria, Adaptive Equalizer Disabled Control bit T1E1 LAC Level < 800 mVpp 0=T1.231 N=175 bits 1=T1/J1 Level < 800 mVpp 1=I.431 N=1544 bits Level < 800 mVpp 0=G.775 N=32 bits 0=E1 Level < 800 ...
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IDT82V2042E 3.6.2 AIS DETECTION The Alarm Indication Signal can be detected by the IDT82V2042E when the Clock & Data Recovery unit is enabled. The status of AIS detection is reflected in the AIS_S bit (STAT0, 16H...). In T1/J1 applications, the ...
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IDT82V2042E 3.7 TRANSMIT AND DETECT INTERNAL PATTERNS The internal patterns (All Ones, All Zeros, PRBS/QRSS pattern and Activate/Deactivate Loopback Code) will be generated and detected by IDT82V2042E. TCLKn is used as the reference clock by default. MCLK can also be ...
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IDT82V2042E 3.8.3 REMOTE LOOPBACK When the RLP bit (MAINT1, 0DH...) is set to ‘1’, the corresponding chan- nel is configured in Remote Loopback mode. In this mode, the recovered clock and data output from Clock and Data Recovery on the ...
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IDT82V2042E LOS/AIS LOSn Detection RCLKn B8ZS/ RDn/RDPn HDB3/AMI CVn/RDNn Decoder Remote Loopback B8ZS/ TCLKn TDn/TDPn HDB3/AMI Encoder TDNn 3.8.4 INBAND LOOPBACK When PATT[1:0] bits (MAINT0, 0CH...) are set to ‘11’, the correspond- ing channel is configured in Inband Loopback mode. ...
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IDT82V2042E 3.8.4.3 Automatic Remote Loopback When ARLP bit (MAINT1, 0DH...) is set to ‘1’, the corresponding chan- nel is configured into the Automatic Remote Loopback mode. In this mode, if the Activate Loopback Code has been detected in the receive ...
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IDT82V2042E 3.9 ERROR DETECTION/COUNTING AND INSERTION 3.9.1 DEFINITION OF LINE CODING ERROR The following line encoding errors can be detected and counted by the IDT82V2042E: • Received Bipolar Violation (BPV) Error: In AMI coding, when two consecutive pulses of the ...
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IDT82V2042E Manual Report mode (CNT_MD=0) counting N A '0' to '1' transition on CNT_TRF? Y CNT0, CNT1 data in counter counter 0 Read the data in CNT0, CNT1 within next round Reset CNT_TRF for the next '0' to '1' transition ...
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IDT82V2042E 3.11 MCLK AND TCLK 3.11.1 MASTER CLOCK (MCLK) MCLK is an independent, free-running reference clock. MCLK is 1.544 MHz for T1/J1 applications and 2.048 MHz in E1 mode. This reference clock is used to generate several internal reference signals: ...
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IDT82V2042E 3.12 MICROCONTROLLER INTERFACES The microcontroller interface provides access to read and write the reg- isters in the device. The chip supports serial microcontroller interface and two kinds of parallel microcontroller interface: Motorola non-Multiplexed mode and Intel non-Multiplexed mode. Different ...
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IDT82V2042E 3.13 INTERRUPT HANDLING All kinds of interrupt of the IDT82V2042E are indicated by the INT pin. When the INT_PIN[0] bit (GCF, 20H) is ‘0’, the INT pin is open drain active low, with a 10 KΩ external pull-up resistor. ...
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IDT82V2042E 3.14 5V TOLERANT I/O PINS All digital input pins will tolerate 5.0 10% volts and are compatible with ± TTL logic. 3.15 RESET OPERATION The chip can be reset in two ways: • Software Reset: Writing to the RST ...
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IDT82V2042E 4 PROGRAMMING INFORMATION 4.1 REGISTER LIST AND MAP The IDT82V2042E registers can be divided into Global Registers and Local Registers. The operation on the Global Registers affects both of the two channels while the operation on Local Registers only ...
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IDT82V2042E Table-20 Per Channel Register List and Map Address (hex) Register R/W CH1 CH2 Transmit and receive termination register 02 22 TERM R/W Jitter attenuation control register 03 23 JACF R/W Transmit path control registers 04 24 TCF0 R/W 05 ...
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IDT82V2042E 4.3 REGISTER DESCRIPTION 4.3.1 GLOBAL REGISTERS Table-21 ID: Device Revision Register (R, Address = 00H) Symbol Bit Default ID[7:0] 7-0 00H Table-22 RST: Reset Register (W, Address = 01H) Symbol Bit Default RST[7:0] 7-0 00H Table-23 GCF: Global Configuration ...
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IDT82V2042E 4.3.2 TRANSMIT AND RECEIVE TERMINATION REGISTER Table-25 TERM: Transmit and Receive Termination Configuration Register (R/W, Address = 02H, 22H) Symbol Bit Default - 7-6 00 T_TERM[2:0] 5-3 000 R_TERM[2:0] 2-0 000 4.3.3 JITTER ATTENUATION CONTROL REGISTER Table-26 JACF: Jitter ...
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IDT82V2042E 4.3.4 TRANSMIT PATH CONTROL REGISTERS Table-27 TCF0: Transmitter Configuration Register 0 (R/W, Address = 04H, 24H) Symbol Bit Default - 7-5 000 T_OFF 4 0 TD_INV 3 0 TCLK_SEL 2 0 T_MD[1:0] 0-1 00 Table-28 TCF1: Transmitter Configuration Register ...
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IDT82V2042E Table-29 TCF2: Transmitter Configuration Register 2 (R/W, Address = 06H, 26H) Symbol Bit Default - 7-6 00 SCAL[5:0] 5-0 100001 Table-30 TCF3: Transmitter Configuration Register 3 (R/W, Address = 07H, 27H) Symbol Bit Default DONE ...
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IDT82V2042E 4.3.5 RECEIVE PATH CONTROL REGISTERS Table-32 RCF0: Receiver Configuration Register 0 (R/W, Address = 09H, 29H) Symbol Bit Default - 7-5 000 R_OFF 4 0 RD_INV 3 0 RCLK_SEL 2 0 R_MD[1:0] 1-0 00 Table-33 RCF1: Receiver Configuration Register ...
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IDT82V2042E Table-34 RCF2: Receiver Configuration Register 2 (R/W, Address = 0BH, 2BH) Symbol Bit Default - 7-6 00 SLICE[1:0] 5 3-2 10 MG[1:0] 1-0 00 4.3.6 NETWORK DIAGNOSTICS CONTROL REGISTERS Table-35 MAINT0: Maintenance Function Control Register 0 (R/W, ...
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IDT82V2042E Table-36 MAINT1: Maintenance Function Control Register 1 (R/W, Address= 0DH, 2DH) Symbol Bit Default - 7-4 0000 ARLP 3 0 RLP 2 0 ALP 1 0 DLP 0 0 Table-37 MAINT2: Maintenance Function Control Register 2 (R/W, Address = ...
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IDT82V2042E Table-39 MAINT4: Maintenance Function Control Register 4 (R/W, Address = 10H, 30H) Symbol Bit Default RIBLBA[7:0] 7-0 (000)00001 Defines the user-programmable receive Inband loopback activate code. The default selection is 00001. Table-40 MAINT5: Maintenance Function Control Register 5 (R/W, ...
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IDT82V2042E 4.3.7 INTERRUPT CONTROL REGISTERS Table-42 INTM0: Interrupt Mask Register 0 (R/W, Address = 13H, 33H) Symbol Bit Default - 7 1 IBLBA_IM 6 1 IBLBD_IM 5 1 PRBS_IM 4 1 TCLK_IM 3 1 DF_IM 2 1 AIS_IM 1 1 ...
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IDT82V2042E Table-43 INTM1: Interrupt Masked Register 1 (R/W, Address = 14H, 34H) Symbol Bit Default DAC_OV_IM 7 1 JAOV_IM 6 1 JAUD_IM 5 1 ERR_IM 4 1 EXZ_IM 3 1 CV_IM 2 1 TIMER_IM 1 1 CNT_IM 0 1 PROGRAMMING ...
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IDT82V2042E Table-44 INTES: Interrupt Trigger Edge Select Register (R/W, Address = 15H, 35H) Symbol Bit Default - 7 0 IBLBA_IES 6 0 IBLBD_IES 5 0 PRBS_IES 4 0 TCLK_IES 3 0 DF_IES 2 0 AIS_IES 1 0 LOS_IES 0 0 ...
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IDT82V2042E 4.3.8 LINE STATUS REGISTERS Table-45 STAT0: Line Status Register 0 (real time status monitor) (R, Address = 16H, 36H) Symbol Bit Default - 7 0 IBLBA_S 6 0 IBLBD_S 5 0 PRBS_S 4 0 TCLK_LOS 3 0 PROGRAMMING INFORMATION ...
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IDT82V2042E Table-45 STAT0: Line Status Register 0 (real time status monitor) (Continued) (R, Address = 16H, 36H) Symbol Bit Default DF_S 2 0 AIS_S 1 0 LOS_S 0 0 Table-46 STAT1: Line Status Register 1 (real time status monitor) (R, ...
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IDT82V2042E 4.3.9 INTERRUPT STATUS REGISTERS Table-47 INTS0: Interrupt Status Register 0 (R, Address = 18H, 38H) (this register is reset and relevant interrupt request is cleared after a read) Symbol Bit Default - 7 0 IBLBA_IS 6 0 IBLBD_IS 5 ...
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IDT82V2042E Table-48 INTS1: Interrupt Status Register 1 (R, Address = 19H, 39H) (this register is reset and the relevant interrupt request is cleared after a read) Symbol Bit Default DAC_OV_IS 7 0 JAOV_IS 6 0 JAUD_IS 5 0 ERR_IS 4 ...
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IDT82V2042E 5 HARDWARE CONTROL PIN SUMMARY Table-51 Hardware Control Pin Summary Pin No. Symbol TQFP 9 MODE1 MODE[1:0]: Operation mode of Control interface select (global control) 10 MODE0 00= Hardware interface 01= Serial interface 10= Parallel - non-Multiplexed - Motorola ...
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IDT82V2042E Table-51 Hardware Control Pin Summary (Continued) Pin No. Symbol TQFP 19 MONT1 MONTn: Receive Monitor n gain select (per channel control) 18 MONT2 In hardware control mode with ternary interface, this pin selects the receive monitor gain for receiver ...
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IDT82V2042E 6 IEEE STD 1149.1 JTAG TEST ACCESS PORT The IDT82V2042E supports the digital Boundary Scan Specification as described in the IEEE 1149.1 standards. The boundary scan architecture consists of data and instruction regis- ters plus a Test Access Port ...
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IDT82V2042E 6.1 JTAG INSTRUCTIONS AND INSTRUCTION REG- ISTER The IR (Instruction Register) with instruction decode block is used to select the test to be executed or the data register to be accessed or both. The instructions are shifted in LSB ...
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IDT82V2042E Table-54 TAP Controller State Description STATE Test Logic Reset In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device initializes the instruction register with the IDCODE instruction. Regardless of the ...
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IDT82V2042E Table-54 TAP Controller State Description (Continued) STATE Exit2-IR This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state, which terminates the ...
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IDT82V2042E 7 TEST SPECIFICATIONS Table-55 Absolute Maximum Rating Symbol VDDA, VDDD Core Power Supply VDDIO I/O Power Supply VDDT1-2 Transmit Power Supply VDDR1-2 Receive Power Supply Input Voltage, Any Digital Pin Input Voltage, Any RTIPn and RRINGn pin Vin ESD ...
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IDT82V2042E Table-56 Recommended Operation Conditions Symbol VDDA,VDDD Core Power Supply VDDIO I/O Power Supply VDDT Transmitter Power Supply VDDR Receive Power Supply TA Ambient operating temperature E1, 75 Ω load E1, 120 Ω Load 1,2,3 Total current dissipation T1, 100 ...
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IDT82V2042E Table-58 DC Characteristics (Continued) Symbol Parameter Output High level Voltage (Iout=400 µ Analog Input Quiescent Voltage (RTIPn, RRINGn MA pin while floating) I Input Leakage Current I TMS, TDI, TRST All other digital input pins ...
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IDT82V2042E Table-60 T1/J1 Receiver Electrical Characteristics Symbol Parameter receiver sensitivity Adaptive Equalizer disabled: Adaptive Equalizer enabled: Analog LOS level Adaptive Equalizer disabled: Adaptive Equalizer enabled: Allowable consecutive zeros before LOS T1.231-1993 I.431 LOS reset Receive Intrinsic Jitter ...
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IDT82V2042E Table-61 E1 Transmitter Electrical Characteristics Symbol Vo-p Output pulse amplitudes E1, 75 Ω load E1, 120 Ω load Vo-s Zero (space) level E1, 75 Ω load E1, 120 Ω load Transmit amplitude variation with supply Difference between pulse sequences ...
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IDT82V2042E Table-62 T1/J1 Transmitter Electrical Characteristics Symbol Vo-p Output pulse amplitudes Vo-s Zero (space) level Transmit amplitude variation with supply Difference between pulse sequences for 17 consecutive pulses (T1.102) TPW Output Pulse Width at 50% of nominal amplitude Pulse width ...
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IDT82V2042E Table-63 Transmitter and Receiver Timing Characteristics Symbol MCLK frequency E1: T1/J1: MCLK tolerance MCLK duty cycle Transmit path TCLK frequency E1: T1/J1: TCLK tolerance TCLK Duty Cycle t1 Transmit Data Setup Time t2 Transmit Data Hold Time Delay time ...
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IDT82V2042E TCLKn TDn/TDPn TDNn RCLKn RDPn/RDn (RCLK_SEL = 0 software mode) (RCLKE = 0 hardware mode) RDNn/CVn RDPn/RDn (RCLK_SEL = 1 software mode) (RCLKE = 1 hardware mode) RDNn/CVn Table-64 Jitter Tolerance Jitter Tolerance E1 – ...
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IDT82V2042E TEST SPECIFICATIONS DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Figure-25 E1 Jitter Tolerance Performance 73 December 12, 2005 ...
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IDT82V2042E Table-65 Jitter Attenuator Characteristics Parameter Jitter Transfer Function Corner (-3dB) Frequency Jitter Attenuator E1: (G.736 400 Hz @ 100 kHz T1/J1: (Per AT&T pub.62411 ...
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IDT82V2042E Table-65 Jitter Attenuator Characteristics (Continued) Parameter 32 bits FIFO: 64 bits FIFO: 128 bits FIFO: Input jitter tolerance before FIFO overflow or underflow 32 bits FIFO: 64 bits FIFO: 128 bits FIFO: TEST SPECIFICATIONS DUAL CHANNEL T1/E1/J1 SHORT HAUL ...
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IDT82V2042E Table-66 JTAG Timing Characteristics Symbol t1 TCK Period t2 TMS to TCK setup Time TDI to TCK Setup Time t3 TCK to TMS Hold Time TCK to TDI Hold Time t4 TCK to TDO Delay Time TEST SPECIFICATIONS DUAL ...
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IDT82V2042E TCK TMS TDI TDO TEST SPECIFICATIONS DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT Figure-29 JTAG Interface Timing 77 December 12, 2005 ...
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IDT82V2042E 8 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS 8.1 SERIAL INTERFACE TIMING Table-67 Serial Interface Timing Characteristics Symbol t1 SCLK High Time t2 SCLK Low Time t3 Active CS to SCLK Setup Time t4 Last SCLK Hold Time to Inactive CS Time ...
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IDT82V2042E 8.2 PARALLEL INTERFACE TIMING Table-68 Non-Multiplexed Motorola Read Timing Characteristics Symbol tRC Read Cycle Time tDW Valid DS Width Delay from DS to Valid Read Signal tRWV R/W tRWH to DS Hold Time tAV Delay from DS to Valid ...
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IDT82V2042E Table-69 Non-Multiplexed Motorola Write Timing Characteristics Symbol tWC Write Cycle Time tDW Valid DS Width tRWV Delay from DS to Valid Write Signal tRWH R Hold Time tAV Delay from DS to Valid Address tAH Address to ...
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IDT82V2042E Table-70 Non-Multiplexed Intel Read Timing Characteristics Symbol tRC Read Cycle Time tRDW Valid RD Width tAV Delay from RD to Valid Address tAH Address to RD Hold Time tPRD RD to Valid Read Data Propagation Delay tDAZ Delay from ...
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IDT82V2042E Table-71 Non-Multiplexed Intel Write Timing Characteristics Symbol tWC Write Cycle Time tWRW Valid WR Width tAV Delay from WR to Valid Address tAH Address to WR Hold Time tDV Delay from WR to Valid Write Data tDHW Write Data ...
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IDT82V2042E ORDERING INFORMATION XXXXXXX IDT Device Type DATASHEET DOCUMENT HISTORY 12/12/2005 pgs. 1, 16, 24, 32, 41, 42, 49, 69, 70, 83 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE ...