82V2042EPF8 IDT, Integrated Device Technology Inc, 82V2042EPF8 Datasheet - Page 10

• Manufacturer Part Number: 82V2042EPF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2042EPF8

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Notes:
1. The footprint ‘n’ (n = 1~2) represents one of the two channels.
2. The name and address of the registers that contain the preceding bit. Only the address of channel 1 register is listed, the rest addresses are represented by ‘...’. Users can find
3. TCLKn missing: the state of TCLKn continues to be high level or low level over 70 MCLK cycles.
2
Table-1 Pin Description
PIN DESCRIPTION
IDT82V2042E
TD1/TDP1
TD2/TDP2
RRING1
RRING2
TRING1
TRING2
TCLK1
TCLK2
Name
TTIP1
TTIP2
RTIP1
RTIP2
TDN1
TDN2
these omitted addresses in the Register Description section.
PIN DESCRIPTION
Analog
Analog
Output
Input
Type
I
I
Pin No.
63
78
62
79
67
74
66
75
37
23
36
24
38
22
TTIPn
These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A logic high
on THZ pin turns all these pins into high impedance state. When THZ bit (TCF1, 03H...)
the corresponding channel is set to high impedance state.
In summary, these pins will become high impedance in the following conditions:
•
•
•
•
•
•
RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 1~2
These signals are the differential receiver inputs.
TDn: Transmit Data for Channel 1~2
When the device is in single rail mode, the NRZ data to be transmitted is input on this pin. Data on TDn pin is sampled into
the device on the active edge of TCLKn and is encoded by AMI, HDB3 or B8ZS line code rules before being transmitted. In
this mode, TDNn should be connected to ground.
TDPn/TDNn: Positive/Negative Transmit Data
When the device is in dual rail mode, the NRZ data to be transmitted for positive/negative pulse is input on these pins. Data
on TDPn/TDNn pin is sampled into the device on the active edge of TCLKn. The active polarity is also selectable. Refer to
3.3.1 TRANSMIT PATH SYSTEM INTERFACE
TCLKn: Transmit Clock for Channel 1~2
This pin inputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode transmit clock. The transmit data at TDn/TDPn or TDNn
is sampled into the device on the active edge of TCLKn. If TCLKn is missing
an interrupt will be generated.
THZ pin is high: all TTIPn/TRINGn enter high impedance;
THZn bit is set to 1: the corresponding TTIPn/TRINGn become high impedance;
Loss of MCLK: all TTIPn/TRINGn pins become high impedance;·
Loss of TCLKn: the corresponding TTIPn/TRINGn become HZ (exceptions: Remote Loopback; Transmit internal pat-
tern by MCLK);
Transmitter path power down: the corresponding TTIPn/TRINGn become high impedance;
After software reset; pin reset and power on: all TTIPn/TRINGn enter high impedance.
1
/TRINGn: Transmit Bipolar Tip/Ring for Channel 1~2
TDPn
0
0
1
1
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
10
for details. The line code in dual rail mode is as follows:
TDNn
0
1
0
1
Description
Space
Positive Pulse
Negative Pulse
Space
Output Pulse
3
and the TCLKn missing interrupt is not masked,
2
is set to ‘1’, the TTIPn/TRINGn in
December 12, 2005