UJA1066TW/3V3,512 NXP Semiconductors, UJA1066TW/3V3,512 Datasheet - Page 60

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UJA1066TW/3V3,512

Manufacturer Part Number
UJA1066TW/3V3,512
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of UJA1066TW/3V3,512

Number Of Transceivers
1
Power Down Mode
Sleep/Standby
Standard Supported
ISO 11898-2
Operating Supply Voltage (min)
5.5V
Operating Temperature (max)
125C
Operating Temperature (min)
-40C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
NXP Semiconductors
Table 27.
T
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
[2]
UJA1066_2
Product data sheet
Symbol
Reset output; pin RSTN
t
t
t
t
Interrupt output; pin INTN
t
Oscillator
f
RSTN(CHT)
RSTN(CLT)
RSTN(INT)
RSTNL
INTN
osc
vj
=
All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient
temperature on wafer level (pretesting). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pretesting
and final testing use correlated test conditions to cover the specified temperature and power supply voltage range.
SPI timing is guaranteed for V
so at these lower voltages a lower maximum SPI communication speed must be observed.
40
°
C to +150
Dynamic characteristics
Parameter
clamped HIGH time,
pin RSTN
clamped LOW time,
pin RSTN
interrupt monitoring time
reset lengthening time
interrupt release
oscillator frequency
°
C; V
BAT42
Fig 21. SPI timing
SDO
SCS
SCK
BAT42
SDI
= 5.5 V to 52 V; V
voltages down to 5 V. For V
floating
…continued
All information provided in this document is subject to legal disclaimers.
X
Conditions
RSTN driven LOW internally
but RSTN pin remains HIGH
RSTN driven HIGH internally
but RSTN pin remains LOW
INTN = 0
after internal or external reset
has been released; RLC = 0
after internal or external reset
has been released; RLC =1
after SPI has read out the
Interrupt register
t
lead
BAT14
Rev. 03 — 17 March 2010
X
t
SCKH
= 5.5 V to 27 V; V
t
su
MSB
T
cyc
BAT42
t
SCKL
MSB
t
h
voltages down to 4.5 V the guaranteed SPI timing values double,
High-speed CAN fail-safe system basis chip
BAT42
[1]
V
BAT14
Min
115
229
229
0.9
18
2
460.8
1 V; unless otherwise specified. All
t
DOV
Typ
-
-
-
-
-
-
512
LSB
t
lag
LSB
UJA1066
© NXP B.V. 2010. All rights reserved.
Max
141
283
283
1.1
22
-
563.2
t
SSH
001aaa405
floating
X
60 of 70
ms
kHz
Unit
ms
ms
ms
ms
μs

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