UJA1066TW/3V3,512 NXP Semiconductors, UJA1066TW/3V3,512 Datasheet - Page 37

• Manufacturer Part Number: UJA1066TW/3V3,512
• Manufacturer: NXP Semiconductors

Specifications of UJA1066TW/3V3,512

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Standard Supported: ISO 11898-2
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 13.
[1]
[2]
UJA1066_2
Product data sheet
Bit
15 and 14
13
12
11 and 10
9
8
7
6 and 5
4 and 3
2 to 0
See
Not supported for the UJA1066TW/3V3 version.
Section
Special Mode register and Special Mode Feedback register bit description
Symbol
A1, A0
RRS
RO
-
ISDM
ERREM
-
WDPRE [1:0]
V1RTHC [1:0] V1 Reset Threshold
-
6.13.1.
Description
register address
Read Register Select
Read Only
reserved
Initialize Software
Development Mode
Error-pin Emulation
Mode
reserved
Watchdog prescaler
Control
reserved
All information provided in this document is subject to legal disclaimers.
[1]
Rev. 03 — 17 March 2010
01
Value
0
1
1
0
0
1
0
1
0
0
00
01
10
11
11
10
01
00
0
Function
select Special Mode register
read the Interrupt Enable Feedback register
read the Special Mode Feedback register
read the register selected by RRS without writing to the
Special Mode register
read the register selected by RRS and write to the
Special Mode register
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
initialization of software development mode
normal watchdog interrupt, reset monitoring and fail-safe
behavior
pin EN reflects the status of the CANFD bits:
pin EN behaves as an enable pin; see
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
watchdog prescale factor 1
watchdog prescale factor 1.5
watchdog prescale factor 2.5
watchdog prescale factor 3.5
V1 reset threshold = 0.9 × V
V1 reset threshold = 0.7 × V
V1 reset threshold = 0.8 × V
V1 reset threshold = 0.9 × V
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
EN is set if CANFD = 0000 (no error)
EN is cleared if CANFD is not 0000 (error)
High-speed CAN fail-safe system basis chip
V1(nom)
V1(nom)
V1(nom)
V1(nom)
[2]
UJA1066
© NXP B.V. 2010. All rights reserved.
Section 6.5.2
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