UJA1066TW/3V3,512 NXP Semiconductors, UJA1066TW/3V3,512 Datasheet - Page 33

• Manufacturer Part Number: UJA1066TW/3V3,512
• Manufacturer: NXP Semiconductors

Specifications of UJA1066TW/3V3,512

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Standard Supported: ISO 11898-2
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 9.
[1]
[2]
UJA1066_2
Product data sheet
Bit
3
2
1
0
This bit is cleared automatically upon each overflow event. It has to be set in software each time the interrupt behavior is required
(fail-safe behavior).
WEN (in the System Configuration register) has to be set to activate the WAKE port function globally.
Interrupt Enable and Interrupt Enable Feedback register bit description
Symbol
WIE
WDRIE
CANIE
-
6.12.7 Interrupt register
The Interrupt register allows the cause of an interrupt event to be determined. The register
is cleared upon a read access and upon any reset event. Hardware ensures that no
interrupt event is lost in case there is a new interrupt forced while reading the register.
After reading the Interrupt register, pin INTN is released for t
event at pin INTN.
The interrupts can be classified into two groups:
•
•
Description
WAKE Interrupt
Enable
Watchdog Restart
Interrupt Enable
CAN Interrupt Enable
reserved
Timing critical interrupts which require immediate reaction (SPI clock count failure
which needs a new SPI command to be resent immediately, and a BAT failure which
needs critical data to be saved immediately into the nonvolatile memory)
Interrupts that do not require an immediate reaction (overtemperature, Ground Shift
and CAN failures, V1, V2 and V3 failures and the wake-ups via CAN and WAKE).
These interrupts will be signalled to the microcontroller once per watchdog period
(maximum) in Normal mode; this avoids overloading the microcontroller with
unexpected interrupt events (e.g. a chattering CAN failure). However, these interrupts
are reflected in the interrupt register
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2010
Value
1
0
1
0
0
0
1
Function
a negative edge at pin WAKE generates an interrupt in
Normal mode, Flash mode or Standby mode
a negative edge at pin WAKE generates a reset in Standby
mode; no interrupt in any other mode
a watchdog restart during watchdog OFF generates an
interrupt
no interrupt forced
CAN-bus event results in a wake-up interrupt in Standby
mode and in Normal or Flash mode (unless CAN is in
Active mode already)
CAN-bus event results in a reset in Standby mode; no
interrupt in any other mode
reserved for SBCs with LIN transceiver
High-speed CAN fail-safe system basis chip
…continued
INTN
to guarantee an edge
UJA1066
© NXP B.V. 2010. All rights reserved.
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