UJA1066TW/3V3,512 NXP Semiconductors, UJA1066TW/3V3,512 Datasheet - Page 32

• Manufacturer Part Number: UJA1066TW/3V3,512
• Manufacturer: NXP Semiconductors

Specifications of UJA1066TW/3V3,512

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Standard Supported: ISO 11898-2
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 8.
[1]
Table 9.
UJA1066_2
Product data sheet
Bit
1 and 0
Bit
15 and 14
13
12
11
10
9
8
7
6
5
4
V2D will be set when V2 is reactivated after a failure. See
System Diagnosis register bit description
Interrupt Enable and Interrupt Enable Feedback register bit description
Symbol
CANMD [1:0] CAN Mode Diagnosis
Symbol
A1, A0
RRS
RO
WTIE
OTIE
GSIE
SPIFIE
BATFIE
VFIE
CANFIE
-
6.12.6 Interrupt Enable register and Interrupt Enable Feedback register
These registers allow the SBC interrupt enable bits to be set, cleared and read back.
Description
register address
Read Register Select
Read Only
Watchdog Time-out
Interrupt Enable
OverTemperature
Interrupt Enable
Ground Shift Interrupt
Enable
SPI clock count Failure
Interrupt Enable
BAT Failure Interrupt
Enable
Voltage Failure Interrupt
Enable
CAN Failure Interrupt
Enable
reserved
Description
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[1]
Rev. 03 — 17 March 2010
Value
01
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
Value
11
10
01
00
Section
…continued
6.6.3.2.
Function
select the Interrupt Enable register
read the Interrupt register
read the Interrupt Enable Feedback register
read the register selected by RRS without writing to
Interrupt Enable register
read the register selected by RRS and write to Interrupt
Enable register
a watchdog overflow during Standby mode causes an
interrupt instead of a reset event (interrupt based cyclic
wake-up feature)
no interrupt forced on watchdog overflow; a reset is forced
instead
exceeding or dropping below the temperature warning limit
causes an interrupt
no interrupt forced
exceeding or dropping below the GND shift limit causes an
interrupt
no interrupt forced
wrong number of CLK cycles (more than, or less than 16)
forces an interrupt; from Start-up mode and Restart mode a
reset is performed instead of an interrupt
no interrupt forced; SPI access is ignored if the number of
cycles does not equal 16
falling edge at SENSE forces an interrupt
no interrupt forced
clearing of V1D, V2D or V3D forces an interrupt
no interrupt forced
any change of the CAN Failure status bits forces an
interrupt
no interrupt forced
reserved for SBCs with LIN transceiver
Function
CAN is in On-line mode
CAN is in On-line Listen mode
CAN is in Off-line mode, or V2 is not active
CAN is in Active mode
High-speed CAN fail-safe system basis chip
UJA1066
© NXP B.V. 2010. All rights reserved.
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