JS28F320J3F75A NUMONYX, JS28F320J3F75A Datasheet - Page 42

• Manufacturer Part Number: JS28F320J3F75A
• Description: PARALLEL NOR
• Manufacturer: NUMONYX

Table 27: STS Configuration Register and Coding Definitions
9.8
9.8.1
Table 28: Block Locking Command Bus-Cycles
Datasheet
42
D[1:0] = STS Configuration Codes
00 = default, level mode;
01 = pulse on Erase Complete
10 = pulse on Program Complete
11 = pulse on Erase or Program Complete
Notes:
1.
2.
3.
Set Block Lock Bit
Clear Block Lock Bits
device ready indication
D7
When configured in one of the pulse modes, STS pulses low with a typical pulse width of 500 ns.
An invalid configuration code will result in both SR.4 and SR.5 being set.
Reserved bits are invalid should be ignored.
Security and Protection
J3 65 nm SBC device offers both hardware and software security features. Block lock
operations, PRs and VPEN allow users to implement various levels of data protection.
Normal Block Locking
J3 65 nm SBC has the capability of Flexible Block Locking (locked blocks remain locked
upon reset or power cycle): All blocks within the device are in unlocked state when ship
from Numonyx. Blocks can be locked individually by issuing the Set Block Lock Bit
command sequence to any address within a block. Once locked, blocks remain locked
when power is removed, or when the device is reset.
All locked blocks are unlocked simultaneously by issuing the Clear Block Lock Bits
command sequence to any device address. Locked blocks cannot be erased or
programmed.
After issuing the Set Block Lock Bit setup command or Clear Block Lock Bits setup
command, the device’s read mode is automatically changed to Read Status Register
mode. After issuing the confirm command, completion of the operation is indicated by
STS (in RY/BY# mode) going high and SR.7 = 1.
Blocks cannot be locked or unlocked while programming or erasing, or while the device
is suspended. Reliable block lock and unlock operations occur only when V
are valid. When V
Command
D6
2
Table 28
D5
PEN
Reserved
≤ V
summarizes the command bus-cycles.
Numonyx
Controls HOLD to a memory controller to prevent accessing a flash memory
subsystem while any flash device's WSM is busy.
Generates a system interrupt pulse when any flash device in an array has
completed a block erase. Helpful for reformatting blocks after file system free
space reclamation or “cleanup.”
Not supported on this device.
Generates system interrupts to trigger servicing of flash arrays when either
erase or program operations are completed, when a common interrupt service
routine is desired.
PENLK
3
Device Address
Block Address
Address Bus
D4
, block lock-bits cannot be changed.
®
Setup Write Cycle
Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
D3
Data Bus
0060h
0060h
Notes
D2
Device Address
Address Bus
Block Address
Confirm Write Cycle
Complete
Pulse on
Program
D1
1
CC
Complete
Data Bus
Pulse on
and V
0001h
00D0h
March 2010
Erase
208032-02
D0
PEN
1