JS28F320J3F75A NUMONYX, JS28F320J3F75A Datasheet - Page 32

• Manufacturer Part Number: JS28F320J3F75A
• Description: PARALLEL NOR
• Manufacturer: NUMONYX

Table 18: Enhanced Configuration Register
Table 19: Asynchronous 8-Word Page Mode Command Bus-Cycle Definition
8.1.2
8.2
Datasheet
32
Set Enhanced Configuration
Register (Set ECR)
ECR
ECR[15:14]
15
1. ECD = Enhanced Configuration Register Data
Reserved
ECR[12:0]
ECR.13
BITS
ECR
Command
14
RFU
RFU
Length
• “1” = 8-Word Page mode
• “0” = 8-Word Page mode (Default)
Output Disable
With CEx asserted, and OE# at a logic-high level (V
Output signals DQ[15:0] are placed in a high-impedance state.
Bus Writes
Writing or Programming to the device, is where the host writes information or data into
the flash device for non-volatile storage. When the flash device is programmed, ‘ones’
are changed to ‘zeros’. ‘Zeros’ cannot be programed back to ‘ones’. To do so, an erase
operation must be performed. Writing commands to the Command User Interface (CUI)
enables various modes of operation, including the following:
Erasing is performed on a block basis – all flash cells within a block are erased together.
Any information or data previously stored in the block will be lost. Erasing is typically
done prior to programming. The Block Erase command requires appropriate command
data and an address within the block to be erased. The Byte/Word Program command
requires the command and address of the location to be written. Set Block Lock-Bit
commands require the command and block within the device to be locked. The Clear
Block Lock-Bits command requires the command and address within the device to be
cleared.
The CUI does not occupy an addressable memory location. It is written when the device
is enabled and WE# is active. The address and data needed to execute a command are
latched on the rising edge of WE# or CE
CE0, CE1, and CE2 that enable the device. CE
pins CE0, CE1, and CE2 that disable the device. See
microprocessor write timings are used.
Page
ECR
• Reading of array data
• Common Flash Interface (CFI) data
• Identifier codes, inspection, and clearing of the Status Register
• Block Erasure, Program, and Lock-bit Configuration (when V
13
ECR
12
Required
Cycles
Bus
2
ECR
11
DESCRIPTION
ECR
10
Numonyx
Oper
Write
ECR
9
First Bus Cycle
®
Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Addr
ECR
8
ECD
(1)
X
ECR
(CE
7
Reserved
X
0060h
X
ECR
Data
low is defined as the combination of pins
6
high is defined as the combination of
IH
All bits should be set to 0.
Either “1” or “0” is for 8-word sense in page
mode.
All bits should be set to 0.
ECR
), the device outputs are disabled.
Table 17 on page
5
Oper
Write
ECR
4
Second Bus Cycle
PEN
ECR
3
NOTES
Addr
= V
ECD
ECR
30). Standard
(1)
2
PENH
)
ECR
1
March 2010
208032-02
0004h
Data
ECR
0