JS28F320J3F75A NUMONYX, JS28F320J3F75A Datasheet - Page 29

• Manufacturer Part Number: JS28F320J3F75A
• Description: PARALLEL NOR
• Manufacturer: NUMONYX

Numonyx
Table 14: Reset Specifications
7.4
Figure 13: AC Input/Output Reference Waveform
Note:
Figure 14: Transient Equivalent Testing Load Circuit
Note:
Table 15: Test Configuration
March 2010
208032-02
Notes:
1.
2.
P1
P2
P3
#
AC test inputs are driven at V
V
C
These specifications are valid for all product versions (packages and speeds).
A reset time, t
CCQ
L
Symbol
®
t
Includes Jig Capacitance
t
t
VCCPH
PHRH
Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
PLPH
/2 V (50% of V
AC Test Conditions
RP# Pulse Low Time
(If RP# is tied to V
specification is not
applicable)
RP# High to Reset during Block Erase, Program, or Lock-Bit
Configuration
Vcc Power Valid to RP# de-assertion (high)
Test Configuration
V
PHQV
CCQ
0.0
V
CCQ
Input
, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
CCQ
= V
). Input rise and fall times (10% to 90%) < 5 ns.
CCQMIN
V
CCQ
CCQ
CC
/2
for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at
, this
Under Test
Device
Parameter
RP# is asserted during block erase,
program or lock-bit configuration
RP# is asserted during read
Test Points
operation
C
L
Out
V
C
Min
100
CCQ
25
60
—
L
30
(pF)
/2
Output
Max
100
—
—
—
Unit
µs
ns
ns
µs
Datasheet
Notes
1,2
—
1
1
29