MT48LC4M16A2P-6:G Micron Technology Inc, MT48LC4M16A2P-6:G Datasheet - Page 66

DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II Tray

MT48LC4M16A2P-6:G

Manufacturer Part Number
MT48LC4M16A2P-6:G
Description
DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC4M16A2P-6:G

Density
64 Mb
Maximum Clock Rate
166 MHz
Package
54TSOP-II
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
5.5 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (4M x 16)
Speed
167MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Organization
4Mx16
Address Bus
14b
Access Time (max)
5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC4M16A2P-6:G
Manufacturer:
MICRON
Quantity:
3 000
Part Number:
MT48LC4M16A2P-6:G
Manufacturer:
MICRON
Quantity:
8 000
Figure 49:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
DQML, DQMH
COMMAND
A0–A9, A11
BA0, BA1
DQM /
CLK
CKE
A10
DQ
t CMS
t CKS
Single WRITE – Without Auto Precharge
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
t CKH
t CMH
Notes:
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
T1
1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <D
3. x16: A8, A9 and A11 = “Don’t Care”
4. PRECHARGE command not allowed or
NOP
DISABLE AUTO PRECHARGE
frequency.
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
t CMS
t CL
COLUMN m 3
t DS
WRITE
BANK
D
T2
IN
t CMH
t CH
t DH
m
t WR
2
NOP 4
T3
66
IN
m> and the PRECHARGE command, regardless of
NOP 4
T4
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RAS would be violated.
SINGLE BANK
PRECHARGE
ALL BANKS
BANK
T5
T6
NOP
t RP
64Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
BANK
ACTIVE
ROW
T7
Timing Diagrams
T8
NOP
DON’T CARE

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