MT48LC4M16A2P-6:G Micron Technology Inc, MT48LC4M16A2P-6:G Datasheet - Page 15

• Manufacturer Part Number: MT48LC4M16A2P-6:G
• Description: DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M16A2P-6:G

• Density: 64 Mb
• Maximum Clock Rate: 166 MHz
• Package: 54TSOP-II
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 5.5 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP II
• Organization: 4Mx16
• Address Bus: 14b
• Access Time (max): 5.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 180mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 6:
Burst Type
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
M8
0
–
M9
0
1
Mode Register Definition
M7
0
–
Programmed Burst Length
M6–M0
Defined
Single Location Access
to ensure compatibility
–
Write Burst Mode
with future devices.
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type
and the starting column address, as shown in Table 5 on page 16.
M11, M10 = “0, 0”
Operating Mode
Standard Operation
All other states reserved
BA0, BA1,
Program
Reserved WB
11
A11
10
A10
M6
0
0
0
0
1
1
1
1
9
A9
M5
Op Mode
0
0
1
1
0
0
1
1
8
A8
M4
0
1
0
1
0
1
0
1
7
A7
15
CAS Latency
6
A6
CAS Latency
5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
3
4
A4
M3
BT
0
1
3
A3
M2
0
0
0
0
1
1
1
1
Burst Length
2
M1
A2
0
0
1
1
0
0
1
1
M0
1
0
1
0
1
0
1
0
1
A1
64Mb: x4, x8, x16 SDRAM
0
A0
Functional Description
Full Page
Reserved
Reserved
Reserved
Burst Type
Interleaved
Sequential
3 = 0
1
2
4
8
Mode Register (Mx)
©2000 Micron Technology, Inc. All rights reserved.
Address Bus
Burst Length
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8