PHT8N06LT,135 NXP Semiconductors, PHT8N06LT,135 Datasheet

MOSFET N-CH 55V 7.5A SOT223

PHT8N06LT,135

Manufacturer Part Number
PHT8N06LT,135
Description
MOSFET N-CH 55V 7.5A SOT223
Manufacturer
NXP Semiconductors
Series
TrenchMOS™r
Datasheet

Specifications of PHT8N06LT,135

Package / Case
SOT-223 (3 leads + Tab), SC-73, TO-261
Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
80 mOhm @ 5A, 5V
Drain To Source Voltage (vdss)
55V
Current - Continuous Drain (id) @ 25° C
7.5A
Vgs(th) (max) @ Id
2V @ 1mA
Gate Charge (qg) @ Vgs
11.2nC @ 5V
Input Capacitance (ciss) @ Vds
650pF @ 25V
Power - Max
1.8W
Mounting Type
Surface Mount
Minimum Operating Temperature
- 55 C
Configuration
Single Dual Drain
Transistor Polarity
N-Channel
Resistance Drain-source Rds (on)
0.08 Ohm @ 5 V
Drain-source Breakdown Voltage
55 V
Gate-source Breakdown Voltage
+/- 13 V
Continuous Drain Current
3.5 A
Power Dissipation
1800 mW
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
934054610135
PHT8N06LT /T3
PHT8N06LT /T3
Philips Semiconductors
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. The device features very
low on-state resistance and has
integral zener diodes giving ESD
protection. It is intended for use in
DC-DC converters and general
purpose switching applications.
PINNING - SOT223
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
ESD LIMITING VALUE
January 1998
TrenchMOS
Logic level FET
SYMBOL
V
V
I
I
I
I
P
P
T
SYMBOL
V
D
D
D
DM
PIN
V
stg
DS
DGR
tot
tot
C
1
2
3
4
GS
, T
j
gate
drain
source
drain (tab)
DESCRIPTION
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Total power dissipation
Storage & operating temperature
PARAMETER
Electrostatic discharge capacitor
voltage
transistor
QUICK REFERENCE DATA
PIN CONFIGURATION
SYMBOL
V
I
P
T
R
D
j
DS
tot
DS(ON)
CONDITIONS
-
R
-
T
On PCB in Fig.2
T
On PCB in Fig.2
T
T
T
On PCB in Fig.2
T
-
CONDITIONS
Human body model
(100 pF, 1.5 k )
1
sp
amb
amb
sp
sp
amb
GS
PARAMETER
Drain-source voltage
Drain current
Total power dissipation
Junction temperature
Drain-source on-state
resistance
= 25 ˚C
= 25 ˚C
= 25 ˚C
= 20 k
= 25 ˚C
= 100 ˚C
= 25 ˚C
1
2
4
3
V
GS
= 5 V
SYMBOL
MIN.
MIN.
- 55
-
-
-
-
-
-
-
-
-
-
g
MAX.
Product specification
150
7.5
1.8
55
80
MAX.
MAX.
150
7.5
3.5
2.2
8.3
1.8
55
55
13
40
2
PHT8N06LT
d
s
Rev 1.100
UNIT
UNIT
UNIT
kV
W
W
˚C
m
V
V
V
A
A
A
A
W
˚C
V
A

Related parts for PHT8N06LT,135

PHT8N06LT,135 Summary of contents

Page 1

Philips Semiconductors TrenchMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting. The device features very low on-state resistance and has integral zener diodes giving ESD protection. ...

Page 2

Philips Semiconductors TrenchMOS transistor Logic level FET THERMAL RESISTANCES SYMBOL PARAMETER R From junction to solder point th j-sp R From junction to ambient th j-amb STATIC CHARACTERISTICS T = 25˚C unless otherwise specified j SYMBOL PARAMETER V Drain-source breakdown ...

Page 3

Philips Semiconductors TrenchMOS transistor Logic level FET AVALANCHE LIMITING VALUE SYMBOL PARAMETER W Drain-source non-repetitive DSS unclamped inductive turn-off energy January 1998 CONDITIONS ...

Page 4

Philips Semiconductors TrenchMOS transistor Logic level FET Normalised Power Derating PD% 120 110 100 Tmb / C Fig.1. Normalised power dissipation. PD% = 100 P ...

Page 5

Philips Semiconductors TrenchMOS transistor Logic level FET 20 ID Tj/C = 150 VGS/V Fig.7. Typical transfer characteristics f conditions parameter ...

Page 6

Philips Semiconductors TrenchMOS transistor Logic level FET 6 VDS/V 5 VDS = 14V QG/nC Fig.13. Typical turn-on gate-charge characteristics f(Q ); conditions parameter V GS ...

Page 7

Philips Semiconductors TrenchMOS transistor Logic level FET PRINTED CIRCUIT BOARD Fig.17. PCB for thermal resistance and power rating for SOT223. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 m thick). January 1998 ...

Page 8

Philips Semiconductors TrenchMOS transistor Logic level FET MECHANICAL DATA Dimensions in mm Net Mass: 0. max Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to ...

Page 9

Philips Semiconductors TrenchMOS transistor Logic level FET DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification ...

Related keywords